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2022-11-14cpukit: Change license to BSD-2 for files with Gaisler copyrightDaniel Cederman2-4/+23
This patch changes the license to BSD-2 for all source files where the copyright is held by Aeroflex Gaisler, Cobham Gaisler, or Gaisler Research. Some files also includes copyright right statements from OAR and/or embedded Brains in addition to Gaisler. Updates #3053.
2022-11-10arm: Fix Armv7-M TLS supportSebastian Huber1-1/+1
Set the thread ID register in the CPU context. Update #3835. Close #4753.
2022-11-09riscv: Simplify _CPU_ISR_Set_level()Sebastian Huber1-15/+13
Where CPU_ENABLE_ROBUST_THREAD_DISPATCH == TRUE, the only supported interrupt level allowed to set is 0 (interrupts enabled). This constraint is enforced by the API level functions which return an error status for other interrupt levels.
2022-11-09riscv: Remove superfluous init/fini functionsSebastian Huber1-12/+0
2022-11-09cpukit/aarch64: Emulate FPSR for FENV trapsKinsey Moore1-0/+20
The AArch64 TRM specifies that when FPCR is set to trap floating point exceptions, the FPSR exception bits are not set. This ensures that FPSR is updated as FENV expects even if floating point exception traps are enabled.
2022-10-14riscv: Move functions to avoid build issuesSebastian Huber1-0/+10
The _RISCV_Map_cpu_index_to_hardid() and _RISCV_Map_hardid_to_cpu_index() functions must be available to all riscv BSPs.
2022-10-14powerpc: Conditionally provide Context_Control_fpSebastian Huber1-3/+6
This avoids a pedantic warning about a zero size Context_Control_fp.
2022-10-14powerpc: Fix 'noreturn' function does returnSebastian Huber1-0/+1
2022-10-14score: Add CPU_THREAD_LOCAL_STORAGE_VARIANTSebastian Huber36-44/+91
Update #3835.
2022-10-14score: Require power of two CPU_STACK_MINIMUM_SIZESebastian Huber3-3/+4
For most CPU ports this was already the case. This makes it possible to use the size as an object alignment using RTEMS_ALIGNED().
2022-09-20bsps/riscv: Add Microchip PolarFire SoC BSP variantPadmarao Begari2-2/+2
The Microchip PolarFire SoC support is implemented as a riscv BSP variant to boot with any individual hart(cpu core) or SMP based on the boot HARTID configurable and support components are 4 CPU Cores (U54), Interrupt controller (PLIC), Timer (CLINT), UART.
2022-09-19Do not use RTEMS_INLINE_ROUTINESebastian Huber41-121/+121
Directly use "static inline" which is available in C99 and later. This brings the RTEMS implementation closer to standard C. Close #3935.
2022-09-09score: Remove _CPU_Counter_difference()Sebastian Huber19-173/+11
All CPU ports used the same _CPU_Counter_difference() implementation. Remove this CPU port interface and mandate a monotonically increasing CPU counter. Close #3456.
2022-09-08powerpc: Add support for VRSAVESebastian Huber3-15/+92
The VRSAVE feature of the Altivec unit can be used to reduce the amount of Altivec registers which need to be saved/restored during interrupt processing and context switches. In order to use the VRSAVE optimization a corresponding multilib (-mvrsave) is required, see GCC configuration. The -mvrsave option must be added to the ABI_FLAGS of the BSP. Currently only the -mcpu=e6500 based QorIQ BSP support this optimization. Update #4712.
2022-08-19cpu.h: Fix gcc 12 warningsRyan Long1-2/+18
Added two pragmas to address, and changed the value of AARCH64_EXCEPTION_MAKE_ENUM_64_BIT to INT_MAX because the old value was not in range of an int. Updates #4662
2022-07-29cpukit/libdl: Add support for AArch64Ryan Long1-0/+256
rtl-mdreloc-aarch64.c and elf_machdep.h came from NetBSD. Updates #4682
2022-07-27Use __asm__ for standard C compatibilitySebastian Huber1-5/+5
2022-07-21aarch64: Use page table level 0Kinsey Moore1-1/+0
This alters the AArch64 page table generation and mapping code and MMU configuration to use page table level 0 in addition to levels 1, 2, and 3. This allows the mapping of up to 48 bits of memory space and is the maximum that can be mapped without relying on additional processor extensions. Mappings are restricted based on the number of physical address bits that the CPU supports.
2022-07-05cpukit/aarch64: Remove _CPU_ISR_install_vectorKinsey Moore2-31/+0
This function was never actually used and is dead code.
2022-07-04score: Add _CPU_Use_thread_local_storage()Sebastian Huber19-0/+202
At some point during system initialization, the idle threads are created. Afterwards, the boot processor basically executes within the context of an idle thread with thread dispatching disabled. On some architectures, the thread-local storage area of the associated thread must be set in dedicated processor registers. Add the new CPU port function to do this: void _CPU_Use_thread_local_storage( const Context_Control *context ) Close #4672.
2022-06-24riscv: Include missing header fileSebastian Huber1-0/+2
2022-06-15score/cpu: Silence ARM and AARCH64 GCC 12 false trigger array warningChris Johns2-1/+7
The false trigger is covered in: GCC 11 and 12 has been patched for constant pointer casts above 4K. This code casts a constant pointer within the first 4K page. As a result the patch disables the warning. Updates #4662
2022-06-08arm: Fix PMSA regions for contiguous sectionsSebastian Huber1-4/+4
Sections with identical attributes may be contiguous with a respective begin and end address which is not on a minimum region boundary. The begin address is aligned down to the region base address. The end address is aligned up to the region end address. Account for this in the check for contiguous sections. Update #4202.
2022-06-08arm: Fix PMSA region mapping with 0x0 end addressSebastian Huber1-1/+1
A section may span up to the end of the address range. In this case the end address is zero. Use the base address to check if a region should be before another region. Update #4202.
2022-06-03arm: Fix typoSebastian Huber1-2/+2
2022-05-04sparc64-syscall.h: Add file headers and licensesRyan Long1-0/+15
This file had no header, copyright, or license. Based on git history, added appropriate copyright and license.
2022-05-04cpukit/microblaze: Add file headers and licensesRyan Long2-0/+70
These files had no file header, copyright, or license. Based on git history, added appropriate copyright and license.
2022-04-08x86_64/elf_machdep.h: Replace stub with NetBSD versionRyan Long1-4/+76
The other ports included that architecture's version of this file from NetBSD. This patch follows that pattern. closes #4641
2022-04-01cpukit/score/cpu/moxie: Change license to BSD-2Joel Sherrill8-24/+176
Permission received from Anthony Green. Updates #3053.
2022-03-24cpukit/: Update Eric Norum contact info and normalize file headersJoel Sherrill1-21/+25
2022-03-12cpukit/aarch64: Add Per_CPU_Control accessorKinsey Moore1-0/+23
Add an architecture-specific implementation for _CPU_Get_current_per_CPU_control() to reduce overhead for getting the current CPU's Per_CPU_Control structure.
2022-03-11arm: Fix PMSA section to region mappingSebastian Huber1-22/+33
Fix move of regions. Allow sections to be contained in a region (may happen due to region alignment).
2022-03-11arm: Add _AArch32_PMSA_Map_sections_to_regions()Sebastian Huber2-20/+90
This simplifies unit testing.
2022-03-10cpukit/: Scripted embedded brains header file clean upJoel Sherrill58-348/+1
Updates #4625.
2022-03-09SMP: Fix start multitasking for some targetsSebastian Huber6-0/+56
The previous SMP multitasking start assumed that the initial heir thread of a processor starts execution in _Thread_Handler(). The _Thread_Handler() sets the interrupt state explicitly by _ISR_Set_level() before it calls the thread entry. Under certain timing conditions, processors may perform an initial context switch to a thread which already executes its thread body (see smptests/smpstart01). In this case, interrupts are disabled after the context switch on targets which do not save/restore the interrupt state during a context switch (aarch64, arm, and riscv). Close #4627.
2022-02-28score/cpu/v850: Change license to BSD-2Joel Sherrill8-24/+176
Updates #3053.
2022-02-28score/cpu/sparc64: Change license to BSD-2Joel Sherrill9-27/+198
2022-02-28score/cpu/sparc: Change license to BSD-2Joel Sherrill16-48/+352
Updates #3053.
2022-02-28score/cpu/powerpc: Change license to BSD-2Joel Sherrill10-34/+219
Updates #3053.
2022-02-28score/cpu/or1k: Change license to BSD-2Joel Sherrill14-42/+308
2022-02-28score/cpu/no_cpu: Change license to BSD-2Joel Sherrill9-27/+198
Updates #3053.
2022-02-28score/cpu/nios2: Change license to BSD-2Joel Sherrill27-81/+594
Updates #3053.
2022-02-28score/cpu/mips: Change license to BSD-2Joel Sherrill6-18/+132
Updates #3053.
2022-02-28score/cpu/m68k: Change license to BSD-2Joel Sherrill8-24/+176
Updates #3053.
2022-02-28score/cpu/i386: Change license to BSD-2Joel Sherrill10-30/+218
sse_test.c was deliberarely NOT changed. Updates #3053.
2022-02-28score/cpu/arm: Change license to BSD-2Joel Sherrill38-115/+836
Updates #3053.
2022-02-25riscv: Use zicsr architecture extensionSebastian Huber5-11/+46
This is required for ISA 2.0 support, see chapter "Zicsr", Control and Status Register (CSR) Instructions, Version 2.0 in RISC-V Instruction Set Manual, Volume I: RISC-V User-Level ISA
2022-02-23score/cpu/i386: Clean up file headers in prep for license change.Joel Sherrill3-6/+9
2022-02-23cpukit/libdebugger: Add MicroBlaze supportKinsey Moore1-0/+24
Add MicroBlaze support for libdebugger. This uses only software break type instructions to provide self-hosted GDB debugging support for applications since internal control of debug hardware is not possible. Also of note, this implementation for MicroBlaze would typically use the brki instruction for software break, but instead uses an illegal opcode to manage software breaks as exceptions. This is due to poor interaction with the debug hardware where the debug hardware will intercept software breaks instead of allowing the software break vector to execute.
2022-02-23microblaze: Decouple exceptions from interruptsKinsey Moore2-8/+8
Exception handling should be enabled at all times during execution to ensure that exceptions are not ignored which would cause further problems. This separates use of the exception enable bit from use of the interrupt enable bit in the machine status register so that they can be manipulated independently.