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Directly use "static inline" which is available in C99 and later. This brings
the RTEMS implementation closer to standard C.
Close #3935.
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All CPU ports used the same _CPU_Counter_difference() implementation. Remove
this CPU port interface and mandate a monotonically increasing CPU counter.
Close #3456.
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The VRSAVE feature of the Altivec unit can be used to reduce the amount of
Altivec registers which need to be saved/restored during interrupt processing
and context switches.
In order to use the VRSAVE optimization a corresponding multilib (-mvrsave) is
required, see GCC configuration. The -mvrsave option must be added to the
ABI_FLAGS of the BSP.
Currently only the -mcpu=e6500 based QorIQ BSP support this optimization.
Update #4712.
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Added two pragmas to address, and changed the value of
AARCH64_EXCEPTION_MAKE_ENUM_64_BIT to INT_MAX because the old value was not
in range of an int.
Updates #4662
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rtl-mdreloc-aarch64.c and elf_machdep.h came from NetBSD.
Updates #4682
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This alters the AArch64 page table generation and mapping code and MMU
configuration to use page table level 0 in addition to levels 1, 2, and
3. This allows the mapping of up to 48 bits of memory space and is the
maximum that can be mapped without relying on additional processor
extensions. Mappings are restricted based on the number of physical
address bits that the CPU supports.
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This function was never actually used and is dead code.
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At some point during system initialization, the idle threads are created.
Afterwards, the boot processor basically executes within the context of an idle
thread with thread dispatching disabled. On some architectures, the
thread-local storage area of the associated thread must be set in dedicated
processor registers. Add the new CPU port function to do this:
void _CPU_Use_thread_local_storage( const Context_Control *context )
Close #4672.
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The false trigger is covered in:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99578
GCC 11 and 12 has been patched for constant pointer casts above
4K. This code casts a constant pointer within the first 4K
page. As a result the patch disables the warning.
Updates #4662
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Sections with identical attributes may be contiguous with a respective
begin and end address which is not on a minimum region boundary. The
begin address is aligned down to the region base address. The end
address is aligned up to the region end address. Account for this in
the check for contiguous sections.
Update #4202.
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A section may span up to the end of the address range. In this case the
end address is zero. Use the base address to check if a region should
be before another region.
Update #4202.
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This file had no header, copyright, or license. Based on git history,
added appropriate copyright and license.
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These files had no file header, copyright, or license. Based on git
history, added appropriate copyright and license.
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The other ports included that architecture's version of this file from
NetBSD. This patch follows that pattern.
closes #4641
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Permission received from Anthony Green.
Updates #3053.
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Add an architecture-specific implementation for
_CPU_Get_current_per_CPU_control() to reduce overhead for getting the
current CPU's Per_CPU_Control structure.
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Fix move of regions. Allow sections to be contained in a region (may
happen due to region alignment).
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This simplifies unit testing.
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Updates #4625.
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The previous SMP multitasking start assumed that the initial heir thread of a
processor starts execution in _Thread_Handler(). The _Thread_Handler() sets
the interrupt state explicitly by _ISR_Set_level() before it calls the thread
entry. Under certain timing conditions, processors may perform an initial
context switch to a thread which already executes its thread body (see
smptests/smpstart01). In this case, interrupts are disabled after the context
switch on targets which do not save/restore the interrupt state during a
context switch (aarch64, arm, and riscv).
Close #4627.
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Updates #3053.
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Updates #3053.
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Updates #3053.
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Updates #3053.
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Updates #3053.
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Updates #3053.
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Updates #3053.
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sse_test.c was deliberarely NOT changed.
Updates #3053.
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Updates #3053.
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This is required for ISA 2.0 support, see chapter
"Zicsr", Control and Status Register (CSR) Instructions, Version 2.0
in
RISC-V Instruction Set Manual, Volume I: RISC-V User-Level ISA
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Add MicroBlaze support for libdebugger. This uses only software break
type instructions to provide self-hosted GDB debugging support for
applications since internal control of debug hardware is not possible.
Also of note, this implementation for MicroBlaze would typically use the
brki instruction for software break, but instead uses an illegal opcode
to manage software breaks as exceptions. This is due to poor interaction
with the debug hardware where the debug hardware will intercept software
breaks instead of allowing the software break vector to execute.
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Exception handling should be enabled at all times during execution to
ensure that exceptions are not ignored which would cause further
problems. This separates use of the exception enable bit from use of the
interrupt enable bit in the machine status register so that they can be
manipulated independently.
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The dispatch code was unnecessarily saving and restoring an extra
interrupt frame. This avoids the extra frame and folds the dispatch call
into a fallthrough to the interrupt frame restoration code.
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Avoid use of magic numbers in favor of named constants and add MSR to
the interrupt frame so that thread dispatch can occur on exceptions as
well.
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Add the functions necessary to support RTEMS_EXCEPTION_EXTENSIONS and
mark this functionality as available on MicroBlaze.
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This patch adds a vector for debug events along with a hook similar to
the exception framework. The debug vector generates an exception frame
for use by libdebugger.
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This patch updates the CPU_Exception_frame to include all necessary
registers, combines hardware snd software exception handlers into a
shared vector, provides an architecture-specific hook for taking
control of exception handling, and moves exception handling over to
actually using the CPU_Exception_frame instead of a minimal interrupt
stack frame. As the significant contents of _exception_handler.S have
been entirely rewritten, the copyright information on this file has been
updated to reflect that.
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This includes fixes and improvements necessary to get libbsd networking
running.
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Use the SRS (Store Return State) instruction if available. This
considerably simplifies the context save and restore.
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On a public interface, the stack pointer must be aligned on an 8-byte
boundary. However, it may temporarily be only aligned on a 4-byte
boundary. The interrupt handling code must ensure that the stack
pointer is properly aligned before it calls a function. See also:
https://developer.arm.com/documentation/den0013/d/Interrupt-Handling/External-interrupt-requests/Nested-interrupt-handling
Update #4579.
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Update #4579.
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Use volatile register r0 for the per-CPU control of the current
processor instead of the non-volatile register r7. This enables the use
of r7 in a follow up patch. Do the interrupt handling in ARM mode.
Update #4579.
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Update #4579.
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