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* Do not use RTEMS_INLINE_ROUTINESebastian Huber2022-09-1941-121/+121
| | | | | | | Directly use "static inline" which is available in C99 and later. This brings the RTEMS implementation closer to standard C. Close #3935.
* score: Remove _CPU_Counter_difference()Sebastian Huber2022-09-0919-173/+11
| | | | | | | All CPU ports used the same _CPU_Counter_difference() implementation. Remove this CPU port interface and mandate a monotonically increasing CPU counter. Close #3456.
* powerpc: Add support for VRSAVESebastian Huber2022-09-083-15/+92
| | | | | | | | | | | | | | The VRSAVE feature of the Altivec unit can be used to reduce the amount of Altivec registers which need to be saved/restored during interrupt processing and context switches. In order to use the VRSAVE optimization a corresponding multilib (-mvrsave) is required, see GCC configuration. The -mvrsave option must be added to the ABI_FLAGS of the BSP. Currently only the -mcpu=e6500 based QorIQ BSP support this optimization. Update #4712.
* cpu.h: Fix gcc 12 warningsRyan Long2022-08-191-2/+18
| | | | | | | | Added two pragmas to address, and changed the value of AARCH64_EXCEPTION_MAKE_ENUM_64_BIT to INT_MAX because the old value was not in range of an int. Updates #4662
* cpukit/libdl: Add support for AArch64Ryan Long2022-07-291-0/+256
| | | | | | rtl-mdreloc-aarch64.c and elf_machdep.h came from NetBSD. Updates #4682
* Use __asm__ for standard C compatibilitySebastian Huber2022-07-271-5/+5
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* aarch64: Use page table level 0Kinsey Moore2022-07-211-1/+0
| | | | | | | | | This alters the AArch64 page table generation and mapping code and MMU configuration to use page table level 0 in addition to levels 1, 2, and 3. This allows the mapping of up to 48 bits of memory space and is the maximum that can be mapped without relying on additional processor extensions. Mappings are restricted based on the number of physical address bits that the CPU supports.
* cpukit/aarch64: Remove _CPU_ISR_install_vectorKinsey Moore2022-07-052-31/+0
| | | | This function was never actually used and is dead code.
* score: Add _CPU_Use_thread_local_storage()Sebastian Huber2022-07-0419-0/+202
| | | | | | | | | | | | At some point during system initialization, the idle threads are created. Afterwards, the boot processor basically executes within the context of an idle thread with thread dispatching disabled. On some architectures, the thread-local storage area of the associated thread must be set in dedicated processor registers. Add the new CPU port function to do this: void _CPU_Use_thread_local_storage( const Context_Control *context ) Close #4672.
* riscv: Include missing header fileSebastian Huber2022-06-241-0/+2
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* score/cpu: Silence ARM and AARCH64 GCC 12 false trigger array warningChris Johns2022-06-152-1/+7
| | | | | | | | | | | | The false trigger is covered in: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99578 GCC 11 and 12 has been patched for constant pointer casts above 4K. This code casts a constant pointer within the first 4K page. As a result the patch disables the warning. Updates #4662
* arm: Fix PMSA regions for contiguous sectionsSebastian Huber2022-06-081-4/+4
| | | | | | | | | | Sections with identical attributes may be contiguous with a respective begin and end address which is not on a minimum region boundary. The begin address is aligned down to the region base address. The end address is aligned up to the region end address. Account for this in the check for contiguous sections. Update #4202.
* arm: Fix PMSA region mapping with 0x0 end addressSebastian Huber2022-06-081-1/+1
| | | | | | | | A section may span up to the end of the address range. In this case the end address is zero. Use the base address to check if a region should be before another region. Update #4202.
* arm: Fix typoSebastian Huber2022-06-031-2/+2
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* sparc64-syscall.h: Add file headers and licensesRyan Long2022-05-041-0/+15
| | | | | This file had no header, copyright, or license. Based on git history, added appropriate copyright and license.
* cpukit/microblaze: Add file headers and licensesRyan Long2022-05-042-0/+70
| | | | | These files had no file header, copyright, or license. Based on git history, added appropriate copyright and license.
* x86_64/elf_machdep.h: Replace stub with NetBSD versionRyan Long2022-04-081-4/+76
| | | | | | | The other ports included that architecture's version of this file from NetBSD. This patch follows that pattern. closes #4641
* cpukit/score/cpu/moxie: Change license to BSD-2Joel Sherrill2022-04-018-24/+176
| | | | | | Permission received from Anthony Green. Updates #3053.
* cpukit/: Update Eric Norum contact info and normalize file headersJoel Sherrill2022-03-241-21/+25
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* cpukit/aarch64: Add Per_CPU_Control accessorKinsey Moore2022-03-121-0/+23
| | | | | | Add an architecture-specific implementation for _CPU_Get_current_per_CPU_control() to reduce overhead for getting the current CPU's Per_CPU_Control structure.
* arm: Fix PMSA section to region mappingSebastian Huber2022-03-111-22/+33
| | | | | Fix move of regions. Allow sections to be contained in a region (may happen due to region alignment).
* arm: Add _AArch32_PMSA_Map_sections_to_regions()Sebastian Huber2022-03-112-20/+90
| | | | This simplifies unit testing.
* cpukit/: Scripted embedded brains header file clean upJoel Sherrill2022-03-1058-348/+1
| | | | Updates #4625.
* SMP: Fix start multitasking for some targetsSebastian Huber2022-03-096-0/+56
| | | | | | | | | | | | | The previous SMP multitasking start assumed that the initial heir thread of a processor starts execution in _Thread_Handler(). The _Thread_Handler() sets the interrupt state explicitly by _ISR_Set_level() before it calls the thread entry. Under certain timing conditions, processors may perform an initial context switch to a thread which already executes its thread body (see smptests/smpstart01). In this case, interrupts are disabled after the context switch on targets which do not save/restore the interrupt state during a context switch (aarch64, arm, and riscv). Close #4627.
* score/cpu/v850: Change license to BSD-2Joel Sherrill2022-02-288-24/+176
| | | | Updates #3053.
* score/cpu/sparc64: Change license to BSD-2Joel Sherrill2022-02-289-27/+198
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* score/cpu/sparc: Change license to BSD-2Joel Sherrill2022-02-2816-48/+352
| | | | Updates #3053.
* score/cpu/powerpc: Change license to BSD-2Joel Sherrill2022-02-2810-34/+219
| | | | Updates #3053.
* score/cpu/or1k: Change license to BSD-2Joel Sherrill2022-02-2814-42/+308
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* score/cpu/no_cpu: Change license to BSD-2Joel Sherrill2022-02-289-27/+198
| | | | Updates #3053.
* score/cpu/nios2: Change license to BSD-2Joel Sherrill2022-02-2827-81/+594
| | | | Updates #3053.
* score/cpu/mips: Change license to BSD-2Joel Sherrill2022-02-286-18/+132
| | | | Updates #3053.
* score/cpu/m68k: Change license to BSD-2Joel Sherrill2022-02-288-24/+176
| | | | Updates #3053.
* score/cpu/i386: Change license to BSD-2Joel Sherrill2022-02-2810-30/+218
| | | | | | sse_test.c was deliberarely NOT changed. Updates #3053.
* score/cpu/arm: Change license to BSD-2Joel Sherrill2022-02-2838-115/+836
| | | | Updates #3053.
* riscv: Use zicsr architecture extensionSebastian Huber2022-02-255-11/+46
| | | | | | | | | | This is required for ISA 2.0 support, see chapter "Zicsr", Control and Status Register (CSR) Instructions, Version 2.0 in RISC-V Instruction Set Manual, Volume I: RISC-V User-Level ISA
* score/cpu/i386: Clean up file headers in prep for license change.Joel Sherrill2022-02-233-6/+9
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* cpukit/libdebugger: Add MicroBlaze supportKinsey Moore2022-02-231-0/+24
| | | | | | | | | | | | Add MicroBlaze support for libdebugger. This uses only software break type instructions to provide self-hosted GDB debugging support for applications since internal control of debug hardware is not possible. Also of note, this implementation for MicroBlaze would typically use the brki instruction for software break, but instead uses an illegal opcode to manage software breaks as exceptions. This is due to poor interaction with the debug hardware where the debug hardware will intercept software breaks instead of allowing the software break vector to execute.
* microblaze: Decouple exceptions from interruptsKinsey Moore2022-02-232-8/+8
| | | | | | | | Exception handling should be enabled at all times during execution to ensure that exceptions are not ignored which would cause further problems. This separates use of the exception enable bit from use of the interrupt enable bit in the machine status register so that they can be manipulated independently.
* cpukit/microblaze: Simplify dispatch assemblyKinsey Moore2022-02-041-45/+3
| | | | | | The dispatch code was unnecessarily saving and restoring an extra interrupt frame. This avoids the extra frame and folds the dispatch call into a fallthrough to the interrupt frame restoration code.
* cpukit/microblaze: Clarify interrupt frame usageKinsey Moore2022-02-042-5/+14
| | | | | | Avoid use of magic numbers in favor of named constants and add MSR to the interrupt frame so that thread dispatch can occur on exceptions as well.
* cpukit/microblaze: Add exception extensionsKinsey Moore2022-02-043-0/+388
| | | | | Add the functions necessary to support RTEMS_EXCEPTION_EXTENSIONS and mark this functionality as available on MicroBlaze.
* cpukit/microblaze: Add debug vector and handlerKinsey Moore2022-02-042-0/+35
| | | | | | This patch adds a vector for debug events along with a hook similar to the exception framework. The debug vector generates an exception frame for use by libdebugger.
* cpukit/microblaze: Add exception frameworkKinsey Moore2022-02-043-17/+187
| | | | | | | | | | | This patch updates the CPU_Exception_frame to include all necessary registers, combines hardware snd software exception handlers into a shared vector, provides an architecture-specific hook for taking control of exception handling, and moves exception handling over to actually using the CPU_Exception_frame instead of a minimal interrupt stack frame. As the significant contents of _exception_handler.S have been entirely rewritten, the copyright information on this file has been updated to reflect that.
* microblaze: Add support for libbsd networkingAlex White2022-02-012-4/+1
| | | | | This includes fixes and improvements necessary to get libbsd networking running.
* arm: Optimize interrupt handlingSebastian Huber2022-01-173-0/+53
| | | | | Use the SRS (Store Return State) instruction if available. This considerably simplifies the context save and restore.
* arm: Fix stack alignment during interrupt handlingSebastian Huber2022-01-171-10/+23
| | | | | | | | | | | On a public interface, the stack pointer must be aligned on an 8-byte boundary. However, it may temporarily be only aligned on a 4-byte boundary. The interrupt handling code must ensure that the stack pointer is properly aligned before it calls a function. See also: https://developer.arm.com/documentation/den0013/d/Interrupt-Handling/External-interrupt-requests/Nested-interrupt-handling Update #4579.
* arm: Avoid duplicate move from CPSRSebastian Huber2022-01-171-4/+3
| | | | Update #4579.
* arm: Rework per-CPU control in interrupt handlingSebastian Huber2022-01-151-56/+46
| | | | | | | | Use volatile register r0 for the per-CPU control of the current processor instead of the non-volatile register r7. This enables the use of r7 in a follow up patch. Do the interrupt handling in ARM mode. Update #4579.
* arm: Use push/pop instructions for readabilitySebastian Huber2022-01-151-11/+11
| | | | Update #4579.
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