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2015-05-30sparc: Disable FPU in interrupt contextAlexander Krutwig2-1/+32
Update #2270.
2015-05-30sparc: Remove superfluous FP enableSebastian Huber2-22/+7
The FP context save/restore makes only sense in the context of FP threads. Update #2270.
2015-05-30sparc: Avoid new window for FP save/restoreSebastian Huber1-54/+48
Update #2270.
2015-05-29sparc: Improve _CPU_Context_validate()Alexander Krutwig1-46/+49
Write the pattern only once to the entry register window and the floating point registers. Update #2270.
2015-05-26sparc: Add static assertionSebastian Huber1-0/+5
2015-05-26sparc: Delete unused CONTEXT_CONTROL_SIZESebastian Huber2-5/+0
2015-05-26sparc: Delete unused ISF_STACK_FRAME_OFFSETSebastian Huber2-3/+0
2015-05-26sparc: Add static offset assertionsSebastian Huber1-0/+32
2015-05-21cpukit: Add Epiphany architecture port v4Hesham ALMatary14-0/+2490
2015-05-21sparc: Add support for sptests/spcontext01Alexander Krutwig4-10/+528
Implement _CPU_Context_validate() and _CPU_Context_volatile_clobber(). Update #2270.
2015-04-17or1k-utility.h: Add missing end of C++ header patternJoel Sherrill1-0/+4
closes 2326.
2015-04-10arm: Align ARM exception frame to 8 bytesDaniel Krueger2-1/+7
The stack pointer must be aligned on 8 byte boundary on ARM, so the size of the exception frame must be a multiple of 8 bytes. Otherwise we might/will get an alignment fault, when executing code in the data abort handler for example. Close #2318. Signed-off-by: Daniel Krueger <daniel.krueger@systec-electronic.com>
2015-04-02or1k: Send halt signal to or1k simulators when rtems terminatesHesham ALMatary2-1/+11
2015-03-25sparc: Ensure interrupt service after ISR enableSebastian Huber1-1/+8
2015-03-20Replace www.rtems.com with www.rtems.orgSebastian Huber2-2/+2
2015-03-16cpukit: add and use CPU_Uint32ptr typeGedare Bloom19-0/+59
2015-03-13score/or1k: Fix warnings. Add missing prototypesHesham ALMatary1-0/+4
Closes #2304
2015-03-11cpukit: Remove old DESCRIPTION: in commentsJoel Sherrill1-6/+4
These were remnants of pre-Doxygen comment style.
2015-03-09or1k/rtems/score/cpu.h: Add no_return attribute to _CPU_Context_restoreJoel Sherrill1-1/+1
2015-03-09cpukit/score/cpu/sh/context.c: Correct name of _CPU_Context_switchJoel Sherrill1-1/+1
2015-03-09or1k: Correct _CPU_Thread_Idle_body prototypeJoel Sherrill2-2/+2
2015-03-05score: Delete unused CPU_UNROLL_ENQUEUE_PRIORITYSebastian Huber19-333/+0
2015-03-04score/cpu/or1k: Add cpuatomic.h to fix broken build.Hesham ALMatary3-2/+19
4e3d9a4d6c76fba8e31138d503f736405dafc213 broke or1k, cpuatomic.h has to be added to all architectures.
2015-03-03or1k/or1k-exception-default.c: Eliminate dependency on BSP provided .h fileHesham ALMatary1-1/+0
2015-02-27ARM: Fix _ARMV4_Exception_fiq_defaultMartin Galvan1-0/+8
In _ARMV4_Exception_fiq_default, set the F bit of the SPSR so that when it gets loaded back to the CPSR in save_more_context it won't re-enable the FIQs. Tested on a TMS570LS3137.
2015-02-23sparc64: fix copyright notices.Gedare Bloom1-12/+1
The sparc64 port had some incorrect copyright notices affixed to source code files.
2015-02-19bfin: do not reset dispatch neededGedare Bloom1-2/+0
Closes #2148 Fix suggested in above ticket. On examination, the assembly appears to be clearing the DISPATCH_NEEDED flag before jumping to _Thread_Dispatch.
2015-02-17score: Add _CPU_SMP_Prepare_start_multitasking()Sebastian Huber5-6/+20
Update #2268.
2015-02-10or1k/cpu.c: Eliminate dependency on BSP provided headerHesham ALMatary1-2/+7
2015-01-20powerpc: Fix AltiVec VSCR save/restoreSebastian Huber3-10/+13
2015-01-13powerpc: AltiVec and FPU context supportSebastian Huber5-8/+700
Add AltiVec and FPU support to the Context_Control in case we use the e6500 multilib. Add PPC_MULTILIB_ALTIVEC and PPC_MULTILIB_FPU multilib defines. Add non-volatile AltiVec and FPU context to Context_Control. Add save/restore of non-volatile AltiVec and FPU to _CPU_Context_switch(). Add save/restore of volatile AltiVec and FPU context to the exception code. Adjust data cache optimizations for the new context and cache line size.
2015-01-13nios2: Disable assembler warningSebastian Huber1-2/+3
Close #2232.
2015-01-09arm: Fix compile error for ARMv6-M multilibSebastian Huber2-2/+5
ARMv6-M is not supported since we cannot directly use the ARMv7-M code due to some inline assembler statements. Close #2231.
2015-01-09powerpc: Add AltiVec register ASM definesSebastian Huber1-0/+32
2015-01-09powerpc: Use PPC_HAS_FPUSebastian Huber1-0/+2
Provide floating point context support only if PPC_HAS_FPU == 1.
2015-01-09powerpc: Add PPC_STACK_ALIGN_POWERSebastian Huber1-16/+6
Simplify PPC_STACK_ALIGNMENT definition.
2015-01-09powerpc: Set PPC_DEFAULT_CACHE_LINE_SIZE for e6500Sebastian Huber2-6/+12
2015-01-09powerpc: Use PPC_DEFAULT_CACHE_LINE_SIZESebastian Huber2-3/+4
Use it for the default PPC_CACHE_ALIGNMENT. Use it for PPC_STRUCTURE_ALIGNMENT.
2015-01-09powerpc: Delete _CPU_IRQ_infoSebastian Huber1-16/+0
2015-01-09powerpc: Use alternate time base for CPU counterSebastian Huber1-3/+3
2014-12-08sparc64: put each copyright on one lineGedare Bloom5-16/+11
2014-12-04i386: doxygen and comments related to VESA real mode framebufferJan Dolezal2-17/+26
2014-12-04SPARC: optimize IRQ enable & disableDaniel Hellstrom1-2/+16
* Coding style cleanups. * Use OS reserved trap 0x89 for IRQ Disable * Use OS reserved trap 0x8A for IRQ Enable * Add to SPARC CPU supplement documentation This will result in faster Disable/Enable code since the system trap handler does not need to decode which function the user wants. Besides the IRQ disable/enabled can now be inline which avoids the caller to take into account that o0-o7+g1-g4 registers are destroyed by trap handler. It was also possible to reduce the interrupt trap handler by five instructions due to this.
2014-11-25arm: Use CPU_TIMESTAMP_USE_STRUCT_TIMESPECSebastian Huber1-1/+1
Converting 64-bit nanoseconds values into the common struct timeval or struct timespec formats requires a 64-bit division to get the seconds value. Performance analysis of high network loads revealed that this is too costly on ARM.
2014-11-20score: i386: functions converting real mode pointer to physical address and backJan Dolezal2-0/+75
2014-10-20cpukit/score/cpu/lm32/irq.c: Fix warningJoel Sherrill1-0/+6
2014-10-20score/cpu/lm32/rtems/score/cpu.h: Fix set but not used warningJoel Sherrill1-0/+3
2014-10-20score/cpu/i386/rtems/score/cpu.h: Fix set but not used warningJoel Sherrill1-0/+1
2014-10-16bfin libcpu and libbsp: Fix warningsJoel Sherrill1-0/+1
2014-10-15h8300/cpu_asm.S: Correct register size suffix for loading DISPATCH_NEEDEDJoel Sherrill1-1/+1
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