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* Fix exception handler for supporting FPUSudarshan Rajagopalan2017-02-151-4/+4
| | | | Close #2401.
* bsps/arm: do not introduce CPU_CACHE_LINE_BYTES in 4.11 and correct ↵Pavel Pisa2016-10-031-4/+2
| | | | CPU_STRUCTURE_ALIGNMENT.
* score/arm: Ensure that copile time alignment is 64 bytes for Cortex-A multilib.Pavel Pisa2016-10-022-2/+11
| | | | | | | | Some/many Cortex-A cores have data cache line length 64 bytes and maximum value has to be used for system structures alignment. Updates #2782 Updates #2783
* arm/score and shared: define ARM hypervisor mode and alternate vector table ↵Pavel Pisa2016-10-021-0/+1
| | | | | | | | | | | base access. The main reason for inclusion of minimum hypervisor related defines is that current ARM boards firmware and loaders (U-boot for example) start loaded operating system kernel in HYP mode to allow it take control of virtualization (Linux/KVM for example). Updates #2783
* score: Fix C/C++ compatibility issueSebastian Huber2016-09-2316-59/+5
| | | | | | | | | Only use CPU_Per_CPU_control if it contains at least one filed. In GNU C empty structures have a size of zero. In C++ structures have a non-zero size. In case CPU_PER_CPU_CONTROL_SIZE is defined to zero, then this structure is not used anymore. Close #2789.
* sparc: Fix context switch on SMPDaniel Cederman2015-11-171-0/+3
| | | | | | | | | | | | | | | | | | We must not load registers (e.g. PSR) from the heir context area before the heir stopped execution. With this patch the write to PSR is divided into two steps. We first update the current window pointer and then we restore the status registers and enable traps. This allows us to move the first write to PSR to be before the write to WIM, as there is now no risk that we get an interrupt where the CWP and WIM would be inconsistent. We only need to make sure that we do not use any of the non-global registers or instructions that affects CWP for three instructions after the write. In the earlier code the non-global %o1 register was used right after the write to PSR, which required the use of three nop:s. Close #2472.
* Fix interrupt epilogue for ARMv7-AR and PowerPCSebastian Huber2015-11-171-0/+27
| | | | Close #2470.
* arm: Replace __sync_synchronize() implementationSebastian Huber2015-09-011-8/+19
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* arm: Use compiler memory barrier by defaultSebastian Huber2015-09-011-1/+7
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* Add __synch_synchronize function for armJan Sommer2015-08-012-0/+10
| | | | Fixes link failure when linking Ada programs on the raspberry pi
* m68k: Include proper header fileSebastian Huber2015-07-241-3/+3
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* arm: Include proper header fileSebastian Huber2015-07-231-3/+3
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* sparc64/rtems/score/cpu.h: Delete dead declarationJoel Sherrill2015-07-161-16/+0
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* powerpc: Do not use the ATB for e500 multilibSebastian Huber2015-07-151-1/+1
| | | | | | The e500v1 has no support for the ATB. Update #2369.
* powerpc: Fix _CPU_Counter_read()Nick Withers2015-07-151-1/+1
| | | | | | The mftb is not available on Book E processors. Use SPR 268 instead. Close #2369.
* powerpc: Add BUCSR register definesSebastian Huber2015-07-081-0/+2
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* score: Simplify <rtems/system.h>Sebastian Huber2015-06-264-2/+4
| | | | | Drop the <rtems/score/percpu.h> include since this file exposes a lot of implementation details.
* arm: Implement _CPU_ISR_Get_level() for ARMv7-MSebastian Huber2015-06-151-3/+3
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* sparc: Add SPARC_USE_SAFE_FP_SUPPORTSebastian Huber2015-06-093-4/+29
| | | | | | | | | | | | | | | | | | | | | | | | The SPARC ABI is a bit special with respect to the floating point context. The complete floating point context is volatile. Thus from an ABI point of view nothing needs to be saved and restored during a context switch. Instead the floating point context must be saved and restored during interrupt processing. Historically the deferred floating point switch is used for SPARC and the complete floating point context is saved and restored during a context switch to the new floating point unit owner. This is a bit dangerous since post-switch actions (e.g. signal handlers) and context switch extensions may silently corrupt the floating point context. The floating point unit is disabled for interrupt handlers. Thus in case an interrupt handler uses the floating point unit then this will result in a trap. On SMP configurations the deferred floating point switch is not supported in principle. So use here a safe floating point support. Safe means that the volatile floating point context is saved and restored around a thread dispatch issued during interrupt processing. Thus post-switch actions and context switch extensions may safely use the floating point unit. Update #2270.
* score: Add Thread_Control::is_fpSebastian Huber2015-06-091-2/+10
| | | | | | | | Store the floating-point unit property in the thread control block regardless of the CPU_HARDWARE_FP and CPU_SOFTWARE_FP settings. Make sure the floating-point unit is only enabled for the corresponding multilibs. This helps targets which have a volatile only floating point context like SPARC for example.
* sparc: Disable FPU in interrupt contextAlexander Krutwig2015-05-302-1/+32
| | | | Update #2270.
* sparc: Remove superfluous FP enableSebastian Huber2015-05-302-22/+7
| | | | | | | The FP context save/restore makes only sense in the context of FP threads. Update #2270.
* sparc: Avoid new window for FP save/restoreSebastian Huber2015-05-301-54/+48
| | | | Update #2270.
* sparc: Improve _CPU_Context_validate()Alexander Krutwig2015-05-291-46/+49
| | | | | | | Write the pattern only once to the entry register window and the floating point registers. Update #2270.
* sparc: Add static assertionSebastian Huber2015-05-261-0/+5
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* sparc: Delete unused CONTEXT_CONTROL_SIZESebastian Huber2015-05-262-5/+0
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* sparc: Delete unused ISF_STACK_FRAME_OFFSETSebastian Huber2015-05-262-3/+0
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* sparc: Add static offset assertionsSebastian Huber2015-05-261-0/+32
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* cpukit: Add Epiphany architecture port v4Hesham ALMatary2015-05-2114-0/+2490
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* sparc: Add support for sptests/spcontext01Alexander Krutwig2015-05-214-10/+528
| | | | | | Implement _CPU_Context_validate() and _CPU_Context_volatile_clobber(). Update #2270.
* or1k-utility.h: Add missing end of C++ header patternJoel Sherrill2015-04-171-0/+4
| | | | closes 2326.
* arm: Align ARM exception frame to 8 bytesDaniel Krueger2015-04-102-1/+7
| | | | | | | | | | | The stack pointer must be aligned on 8 byte boundary on ARM, so the size of the exception frame must be a multiple of 8 bytes. Otherwise we might/will get an alignment fault, when executing code in the data abort handler for example. Close #2318. Signed-off-by: Daniel Krueger <daniel.krueger@systec-electronic.com>
* or1k: Send halt signal to or1k simulators when rtems terminatesHesham ALMatary2015-04-022-1/+11
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* sparc: Ensure interrupt service after ISR enableSebastian Huber2015-03-251-1/+8
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* Replace www.rtems.com with www.rtems.orgSebastian Huber2015-03-202-2/+2
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* cpukit: add and use CPU_Uint32ptr typeGedare Bloom2015-03-1619-0/+59
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* score/or1k: Fix warnings. Add missing prototypesHesham ALMatary2015-03-131-0/+4
| | | | Closes #2304
* cpukit: Remove old DESCRIPTION: in commentsJoel Sherrill2015-03-111-6/+4
| | | | These were remnants of pre-Doxygen comment style.
* or1k/rtems/score/cpu.h: Add no_return attribute to _CPU_Context_restoreJoel Sherrill2015-03-091-1/+1
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* cpukit/score/cpu/sh/context.c: Correct name of _CPU_Context_switchJoel Sherrill2015-03-091-1/+1
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* or1k: Correct _CPU_Thread_Idle_body prototypeJoel Sherrill2015-03-092-2/+2
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* score: Delete unused CPU_UNROLL_ENQUEUE_PRIORITYSebastian Huber2015-03-0519-333/+0
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* score/cpu/or1k: Add cpuatomic.h to fix broken build.Hesham ALMatary2015-03-043-2/+19
| | | | | 4e3d9a4d6c76fba8e31138d503f736405dafc213 broke or1k, cpuatomic.h has to be added to all architectures.
* or1k/or1k-exception-default.c: Eliminate dependency on BSP provided .h fileHesham ALMatary2015-03-031-1/+0
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* ARM: Fix _ARMV4_Exception_fiq_defaultMartin Galvan2015-02-271-0/+8
| | | | | | | | In _ARMV4_Exception_fiq_default, set the F bit of the SPSR so that when it gets loaded back to the CPSR in save_more_context it won't re-enable the FIQs. Tested on a TMS570LS3137.
* sparc64: fix copyright notices.Gedare Bloom2015-02-231-12/+1
| | | | | The sparc64 port had some incorrect copyright notices affixed to source code files.
* bfin: do not reset dispatch neededGedare Bloom2015-02-191-2/+0
| | | | | | | | Closes #2148 Fix suggested in above ticket. On examination, the assembly appears to be clearing the DISPATCH_NEEDED flag before jumping to _Thread_Dispatch.
* score: Add _CPU_SMP_Prepare_start_multitasking()Sebastian Huber2015-02-175-6/+20
| | | | Update #2268.
* or1k/cpu.c: Eliminate dependency on BSP provided headerHesham ALMatary2015-02-101-2/+7
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* powerpc: Fix AltiVec VSCR save/restoreSebastian Huber2015-01-203-10/+13
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