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2018-11-12arm: Remove use of proc_ptrSebastian Huber3-14/+16
Update #3585.
2018-11-12no_cpu: Remove use of proc_ptrSebastian Huber2-24/+35
Update #3585.
2018-11-12x86_64: Remove duplicate _CPU_Thread_Idle_body()Sebastian Huber1-5/+0
2018-11-12m32c: Remove this targetSebastian Huber13-1605/+0
Update #3599.
2018-11-08h8300: Remove left over filesSebastian Huber2-61/+0
Update #2452.
2018-11-08score: Remove _ISR_Dispatch()Sebastian Huber9-136/+14
This function was only used on some m68k variants. On these m68k variants there is no need to use a global symbol. Use a local label instead. Remove _ISR_Dispatch() from the architecture-independent layer.
2018-11-08score: Rename interrupt stack symbolsSebastian Huber1-1/+1
Rename * _Configuration_Interrupt_stack_area_begin in _ISR_Stack_area_begin, * _Configuration_Interrupt_stack_area_end in _ISR_Stack_area_end, and * _Configuration_Interrupt_stack_size in _ISR_Stack_size. Move definitions to <rtems/score/isr.h>. The new names are considerable shorter and in the right namespace. Update #3459.
2018-10-10build: Include header.am in cpukit/Makefile.amSebastian Huber40-363/+148
Include all cpukit/*/header.am files in cpukit/Makefile.am. This gets rid of all subtree Makefile.am and the sudirs hack.
2018-10-10build: Remove local.amSebastian Huber1-1/+0
2018-10-10build: Merge score/cpu/*/Makefile.amSebastian Huber19-271/+0
2018-10-09build: Remove specialized CPPFLAGSSebastian Huber17-20/+0
2018-10-05score: Remove CPU_PROVIDES_IDLE_THREAD_BODYSebastian Huber33-482/+52
Remove the CPU_PROVIDES_IDLE_THREAD_BODY option to avoid unnecessary conditional compilation. Close #3539.
2018-10-04Rename files to make them unique within cpukitSebastian Huber2-1/+1
This allows to build librtemscpu.a in one rush in the future.
2018-10-02Use rtems_task_exit()Sebastian Huber1-1/+1
Update #3530. Update #3533.
2018-09-20sparc: clang AS does no accept UNIMP without argumentDaniel Hellstrom1-1/+1
2018-09-20sparc: Remove sequence that could trigger B2BST errataDaniel Cederman1-2/+0
2018-09-20sparc: Return to previous section type when done with .data._SPARC_CounterDaniel Cederman1-0/+1
2018-09-17powerpc: Fix _CPU_Counter_read() for MPC860Sebastian Huber1-0/+2
The mpc860 is a RTEMS-specific multilib define, see GCC "gcc/config/rs6000/rtems.h".
2018-08-29rtems/score/epiphany-utility.h: Fix not a prototype warningJoel Sherrill1-1/+1
2018-08-29score/cpu/bfin/cpu.c: Fix _CPU_Thread_Idle_body() prototypeJoel Sherrill1-1/+1
2018-08-24sparc: Restore npc when returning from the syscall_lazy_fp_switch trapDaniel Cederman1-1/+1
If the floating point trap occurred in a delay slot it is not certain that npc will be equal to pc + 4.
2018-08-13bsps/x86_64: Add APIC timer based clock driverAmaan Cheval1-0/+23
The APIC timer is calibrated by running the i8254 PIT for a fraction of a second (determined by PIT_CALIBRATE_DIVIDER) and counting how many times the APIC counter has ticked. The calibration can be run multiple times (determined by APIC_TIMER_NUM_CALIBRATIONS) and averaged out. Updates #2898.
2018-08-13bsps/x86_64: Add support for RTEMS interruptsAmaan Cheval6-33/+250
Updates #2898.
2018-08-13bsps/x86_64: Add paging support with 1GiB super pagesAmaan Cheval1-0/+13
Updates #2898.
2018-08-13bsps/x86_64: Reorganize header files and compile-optionsAmaan Cheval7-22/+81
Updates #2898.
2018-08-02score: Remove CPU_PARTITION_ALIGNMENTSebastian Huber19-216/+0
Use the CPU_SIZEOF_POINTER alignment instead. The internal alignment requirement is defined by the use of Chain_Node (consisting of two pointers) to manage the free chain of partitions. It seems that previously the condition CPU_PARTITION_ALIGNMENT >= sizeof(Chain_Node) was true on all CPU ports. Now, we need an additional check. Update #3482.
2018-08-02riscv: Fix CPU_ALIGNMENTSebastian Huber1-1/+3
Update #3433.
2018-07-27riscv: Rework CPU counter supportSebastian Huber4-5/+91
Update #3433.
2018-07-25riscv: Add CLINT and PLIC supportSebastian Huber1-5/+45
The CLINT and PLIC need some per-processor state. Update #3433.
2018-07-25riscv: Use wfi instruction for idle taskSebastian Huber2-12/+3
Update #3433.
2018-07-25riscv: Rework exception handlingSebastian Huber6-144/+54
Remove _CPU_ISR_install_raw_handler() and _CPU_ISR_install_vector() functions. Applications can install an exception handler via the fatal error handler to handle synchronous exceptions. Handle interrupt exceptions via _RISCV_Interrupt_dispatch() which must be provided by the BSP. Update #3433.
2018-07-25riscv: New CPU_Exception_frameSebastian Huber4-64/+203
Use the CPU_Interrupt_frame for the volatile context. Add non-volatile registers and extra state on top of it. Update #3433.
2018-07-25riscv: Add exception codesSebastian Huber1-0/+39
Update #3433.
2018-07-25powerpc: Fix _CPU_Instruction_illegal()Sebastian Huber1-1/+1
Apparently the .word assembler directive is not the right thing on this target.
2018-07-23score: Add _CPU_Instruction_illegal()Sebastian Huber19-0/+100
On some architectures/simulators it is difficult to provoke an exception with misaligned or illegal data loads. Use an illegal instruction instead. Update #3433.
2018-07-20score: Add _CPU_Instruction_no_operation()Sebastian Huber19-0/+100
This helps to reduce the use of architecture-specific defines throughout the code base.
2018-07-20score: Move context validation declarationsSebastian Huber38-203/+199
The context validation support functions _CPU_Context_validate() and _CPU_Context_volatile_clobber() are used only by one test program (spcontext01). Move the function declarations to the CPU port implementation header file.
2018-07-20score: Remove obsolete CPU port definesSebastian Huber3-34/+0
2018-07-11x86_64/console: Add NS16550 polled console driverAmaan Cheval2-0/+17
This addition allows us to successfully run the sample hello.exe test. Updates #2898.
2018-07-11bsp/x86_64: Minimal bootable BSPAmaan Cheval11-0/+893
Current state: - Basic context initialization and switching code. - Stubbed console (empty functions). - Mostly functional linker script (may need tweaks if we ever want to move away from the large code model (see: CPU_CFLAGS). - Fully functional boot, by using FreeBSD's bootloader to load RTEMS's ELF for UEFI-awareness. In short, the current state with this commit lets us boot, go through the system initialization functions, and then call user application's Init task too. Updates #2898.
2018-07-06riscv: Add LADDR assembler defineSebastian Huber2-2/+12
An address must be loaded to a register according to the code model. Add LADDR define for use in assembler code. Update #3433.
2018-07-06riscv: Implement CPU counterSebastian Huber2-2/+16
Update #3433.
2018-07-05riscv: Clear reservationsSebastian Huber5-6/+25
See also RISC-V User-Level ISA V2.3, comment in section 8.2 "Load-Reserved/Store-Conditional Instructions". Update #3433.
2018-07-02riscv: Fix fcsr initializationSebastian Huber2-1/+19
Update #3433.
2018-06-29riscv: Fix SMP context switch supportSebastian Huber1-2/+2
Update #3433.
2018-06-29riscv: Add SMP context switch supportSebastian Huber1-0/+47
Update #3433.
2018-06-29riscv: Add floating-point supportSebastian Huber8-50/+538
Update #3433.
2018-06-29riscv: Fix global constructionSebastian Huber1-4/+5
Update #3433.
2018-06-29riscv: Add TLS supportSebastian Huber2-0/+9
Update #3433.
2018-06-29riscv: Remove dead codeSebastian Huber1-41/+1
Update #3433.
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