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The embedded brains GmbH & Co. KG is the legal successor of embedded
brains GmbH.
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Update #3835.
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Updates #3053.
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Statically initialize the trap table in start.S to jump to _SPARC_Bad_trap()
for all unexpected traps. This enables a proper RTEMS fatal error handling
right from the start. Do not rely on the stack and register settings which
caused an unexpected trap. Use the ISR stack of the processor to do the fatal
error handling. Save the full context which caused the trap. Fatal error
handler may use it for error logging.
Unify the _CPU_Exception_frame_print() implementations and move it to cpukit.
Update #4459.
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Move _CPU_ISR_install_raw_handler() and _CPU_ISR_install_vector() to separate
files. The goal is to make their use optional.
Update #4458.
Update #4459.
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Update #3585.
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This function was only used on some m68k variants. On these m68k
variants there is no need to use a global symbol. Use a local label
instead.
Remove _ISR_Dispatch() from the architecture-independent layer.
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The definition of _CPU_Trap_slot_template is BSP-independent. A
potential para-virtualization support may use <rtems/score/paravirt.h>.
This patch is a part of the BSP source reorganization.
Update #3285.
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The SPARC ABI is a bit special with respect to the floating point context.
The complete floating point context is volatile. Thus, from an ABI point
of view nothing needs to be saved and restored during a context switch.
Instead the floating point context must be saved and restored during
interrupt processing. Historically, the deferred floating point switch was
used for SPARC and the complete floating point context is saved and
restored during a context switch to the new floating point unit owner.
This is a bit dangerous since post-switch actions (e.g. signal handlers)
and context switch extensions may silently corrupt the floating point
context.
The floating point unit is disabled for interrupt handlers. Thus, in case
an interrupt handler uses the floating point unit then this will result in a
trap (INTERNAL_ERROR_ILLEGAL_USE_OF_FLOATING_POINT_UNIT).
In uniprocessor configurations, a lazy floating point context switch is
used. In case an active floating point thread is interrupted (PSR[EF] == 1)
and a thread dispatch is carried out, then this thread is registered as the
floating point owner. When a floating point owner is present during a
context switch, the floating point unit is disabled for the heir thread
(PSR[EF] == 0). The floating point disabled trap checks that the use of the
floating point unit is allowed and saves/restores the floating point context
on demand.
Update #3077.
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Rename SPARC_USE_SAFE_FP_SUPPORT in SPARC_USE_SYNCHRONOUS_FP_SWITCH.
Update comment.
Update #3077.
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Update #2751.
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Update #2809.
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Move CPU_Interrupt_frame related defines to <rtems/score/cpuimpl.h>.
Update #2809.
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Rename SPARC-specific CPU_Minimum_stack_frame to
SPARC_Minimum_stack_frame. Rename SPARC-specific
CPU_MINIMUM_STACK_FRAME_SIZE to SPARC_MINIMUM_STACK_FRAME_SIZE.
Update #2809.
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Update #2559.
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We must not load registers (e.g. PSR) from the heir context area before
the heir stopped execution.
With this patch the write to PSR is divided into two steps. We first update
the current window pointer and then we restore the status registers and
enable traps. This allows us to move the first write to PSR to be before
the write to WIM, as there is now no risk that we get an interrupt where
the CWP and WIM would be inconsistent. We only need to make sure that we
do not use any of the non-global registers or instructions that affects
CWP for three instructions after the write.
In the earlier code the non-global %o1 register was used right after the
write to PSR, which required the use of three nop:s.
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The SPARC ABI is a bit special with respect to the floating point context.
The complete floating point context is volatile. Thus from an ABI point
of view nothing needs to be saved and restored during a context switch.
Instead the floating point context must be saved and restored during
interrupt processing. Historically the deferred floating point switch is
used for SPARC and the complete floating point context is saved and
restored during a context switch to the new floating point unit owner.
This is a bit dangerous since post-switch actions (e.g. signal handlers)
and context switch extensions may silently corrupt the floating point
context. The floating point unit is disabled for interrupt handlers.
Thus in case an interrupt handler uses the floating point unit then this
will result in a trap.
On SMP configurations the deferred floating point switch is not
supported in principle. So use here a safe floating point support. Safe
means that the volatile floating point context is saved and restored
around a thread dispatch issued during interrupt processing. Thus
post-switch actions and context switch extensions may safely use the
floating point unit.
Update #2270.
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Update #2270.
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The FP context save/restore makes only sense in the context of FP
threads.
Update #2270.
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Changes to the trap table might be missed by other cores.
If the system state is up, the other cores can be notified
using SMP messages that they need to flush their icache.
If the up state has not been reached there is no need to
notify other cores. They will do an automatic flush of the
icache just after entering the up state, but before enabling
interrupts. Cache invalidation is required for both single
and multiprocessor systems.
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Guest systems in paravirtualization environments run usually in user
mode. Thus it is not possible to directly access the PSR and TBR
registers. Use functions instead of inline assembler to access these
registers if RTEMS_PARAVIRT is defined.
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We must not alter the is executing indicator in
_CPU_Context_Initialize() since this would cause an invalid state during
a self restart.
The is executing indicator must be valid at creation time since
otherwise _Thread_Kill_zombies() uses an undefined value for not started
threads. This could result in a system life lock.
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The current implementation of task migration in RTEMS has some
implications with respect to the interrupt latency. It is crucial to
preserve the system invariant that a task can execute on at most one
processor in the system at a time. This is accomplished with a boolean
indicator in the task context. The processor architecture specific
low-level task context switch code will mark that a task context is no
longer executing and waits that the heir context stopped execution
before it restores the heir context and resumes execution of the heir
task. So there is one point in time in which a processor is without a
task. This is essential to avoid cyclic dependencies in case multiple
tasks migrate at once. Otherwise some supervising entity is necessary to
prevent life-locks. Such a global supervisor would lead to scalability
problems so this approach is not used. Currently the thread dispatch is
performed with interrupts disabled. So in case the heir task is
currently executing on another processor then this prolongs the time of
disabled interrupts since one processor has to wait for another
processor to make progress.
It is difficult to avoid this issue with the interrupt latency since
interrupts normally store the context of the interrupted task on its
stack. In case a task is marked as not executing we must not use its
task stack to store such an interrupt context. We cannot use the heir
stack before it stopped execution on another processor. So if we enable
interrupts during this transition we have to provide an alternative task
independent stack for this time frame. This issue needs further
investigation.
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Use register g6 for the per-CPU control of the current processor. The
register g6 is reserved for the operating system by the SPARC ABI. On
Linux register g6 is used for a similar purpose with the same method
since 1996.
The register g6 must be initialized during system startup and then must
remain unchanged.
Since the per-CPU control is used in all critical sections of the
operating system, this is a performance optimization for the operating
system core procedures. An additional benefit is that the low-level
context switch and interrupt processing code is now identical on non-SMP
and SMP configurations.
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The registers g2 through g4 are reserved for applications. GCC uses
them as volatile registers by default. So they are treated like
volatile registers in RTEMS as well.
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The _CPU_Context_switch() is a normal function call. The following
registers are volatile (the caller must assume that the register
contents are destroyed by the callee) according to "SYSTEM V APPLICATION
BINARY INTERFACE - SPARC Processor Supplement", Third Edition: g1, o0,
o1, o2, o3, o4, o5. Drop these registers from the context.
Ensure that offset defines match the structure offsets.
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Tested and implemented on ARM, m68k, PowerPC and SPARC. Other
architectures need more work.
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This variable must be available for each processor in the system.
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This patch is a task from GCI 2012 which improves the Doxygen
comments in the RTEMS source.
https://google-melange.appspot.com/gci/task/view/google/gci2012/7977211
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Script does what is expected and tries to do it as
smartly as possible.
+ remove occurrences of two blank comment lines
next to each other after Id string line removed.
+ remove entire comment blocks which only exited to
contain CVS Ids
+ If the processing left a blank line at the top of
a file, it was removed.
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* cpu.c: Remove /*PAGE markers which were interpreted by a long dead
print script.
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* cpu.c: Remove unused variable reported by clang.
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* cpu.c, cpu_asm.S: Add include of config.h
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* cpu.c, rtems/score/cpu.h: Eliminate _CPU_Thread_dispatch_pointer and
passing address of _Thread_Dispatch to _CPU_Initialize. Clean up
comments.
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* cpu.c: Remove extraneous spaces.
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PR 1278/cpukit
* cpu.c: Fix incorrect bit manipulation on returning old address of raw
trap handler.
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* cpu.c, rtems/score/cpu.h: Move interrupt_stack_size field from CPU
Table to Configuration Table. Eliminate CPU Table from all ports.
Delete references to CPU Table in all forms.
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* score/cpu/sparc/cpu.c, score/cpu/sparc/rtems/score/cpu.h,
score/include/rtems/score/context.h, score/src/threadhandler.c: Fix
stack so gdb backtrace does not print corrupted frame message after
_Thread_Handler. Daniel Hellstrom <daniel@gaisler.com> provided the
SPARC implementation and I made it more general.
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* score/cpu/arm/cpu.c, score/cpu/avr/cpu.c, score/cpu/bfin/cpu.c,
score/cpu/c4x/cpu.c, score/cpu/h8300/cpu.c, score/cpu/i386/cpu.c,
score/cpu/m68k/cpu.c, score/cpu/mips/cpu.c, score/cpu/nios2/cpu.c,
score/cpu/no_cpu/cpu.c, score/cpu/sh/cpu.c, score/cpu/sparc/cpu.c,
cpukit/sapi/src/exinit.c: Move copying of CPU Table to shared
executive initialization.
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PR 1237/rtems
* cpu.c, cpu_asm.S, rtems/score/cpu.h: Add logic to prevent stack creep
when interrupts occur at a sufficient rate that the interrupted
thread never gets to clean its stack. This patch ensures that an
interrupted thread will not nest ISR dispatches on its stack.
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* cpu.c, rtems/score/cpu.h, rtems/score/sparc.h: Convert to using
c99 fixed size types.
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