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* score: Introduce _Internal_error()Sebastian Huber2016-12-121-1/+1
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* score: Remove fatal is internal indicatorSebastian Huber2016-12-091-5/+1
| | | | | | | | | The fatal is internal indicator is redundant since the fatal source and error code uniquely identify a fatal error. Keep the fatal user extension is internal parameter for backward compatibility and set it to false always. Update #2825.
* score: Robust thread dispatchSebastian Huber2016-11-231-0/+2
| | | | | | | | | | | | On SMP configurations, it is a fatal error to call blocking operating system with interrupts disabled, since this prevents delivery of inter-processor interrupts. This could lead to executing threads which are not allowed to execute resulting in undefined behaviour. The ARM Cortex-M port has a similar problem, since the interrupt state is not a part of the thread context. Update #2811.
* score: Add _ISR_Is_enabled()Sebastian Huber2016-11-181-0/+5
| | | | | | | In contrast to _ISR_Get_level() the _ISR_Is_enabled() function evaluates a level parameter and returns a boolean value. Update #2811.
* powerpc: Use Per_CPU_Control::isr_dispatch_disableSebastian Huber2016-11-182-2/+5
| | | | Update #2751.
* powerpc: Add up to date CPU_Interrupt_frameSebastian Huber2016-11-182-6/+386
| | | | | | | Rename ppc_exc_min_frame to CPU_Interrupt_frame. Move it and the corresponding defines to <rtems/score/cpuimpl.h>. Update #2809.
* powerpc: Move legacy CPU_Interrupt_frameSebastian Huber2016-11-181-31/+0
| | | | | | | The only remaining user of CPU_Interrupt_frame on PowerPC is the mpc5xx support. Move it to here. Update #2809.
* rtems: Conditionally define rtems_interrupt_frameSebastian Huber2016-11-181-1/+1
| | | | Update #2808.
* score: Move CPU_PER_CPU_CONTROL_SIZESebastian Huber2016-11-182-3/+3
| | | | | Move CPU_PER_CPU_CONTROL_SIZE and the optional CPU_Per_CPU_control to <rtems/score/cpuimpl.h> to hide it from <rtems.h>.
* score: Remove obsolete definesSebastian Huber2016-11-181-19/+0
| | | | The thread dispatch inline option is no longer used.
* powerpc: Add _CPU_Get_current_per_CPU_control()Sebastian Huber2016-11-101-0/+27
| | | | | | | | Add _CPU_Get_current_per_CPU_control() on SMP configurations. Use SPRG0 for the current per-CPU control. This reduces the code size by three instructions and is slightly faster. Update #2805.
* score: Add <rtems/score/cpuimpl.h>Sebastian Huber2016-11-073-0/+35
| | | | | | The aim of this file is to encapsulate CPU port implementation details. This helps to hide implementation details from <rtems.h> which indirectly includes <rtems/score/cpu.h>.
* score: Fix C/C++ compatibility issueSebastian Huber2016-09-231-4/+0
| | | | | | | Only use CPU_Per_CPU_control if it contains at least one filed. In GNU C empty structures have a size of zero. In C++ structures have a non-zero size. In case CPU_PER_CPU_CONTROL_SIZE is defined to zero, then this structure is not used anymore.
* stackchk: Use a const pattern to checkSebastian Huber2016-09-081-1/+9
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* score: Simplify priority bit map implementationSebastian Huber2016-06-082-2/+2
| | | | | | | | | | The priority bit map can deal with a maximum of 256 priority values ranging from 0 to 255. Consistently use an unsigned int for computation, due to the usual integer promotion rules. Make Priority_bit_map_Word definition architecture-independent and define it to uint16_t. This was already the case for all architectures except PowerPC. Adjust the PowerPC bitmap support accordingly.
* score: Delete CPU_USE_GENERIC_BITFIELD_DATASebastian Huber2016-06-081-2/+0
| | | | | | Rename __log2table into _Bitfield_Leading_zeros since it acually returns the count of leading zeros of an 8-bit integer. The value for zero is a bit odd. Provide it unconditionally.
* powerpc: Define bitmap defines to FALSESebastian Huber2016-06-081-0/+4
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* powerpc: Add FSL_EIS_TENSR, etc. definesSebastian Huber2016-04-221-0/+7
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* powerpc: Add FSL_EIS_MAS8Sebastian Huber2016-04-131-0/+2
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* score: Add CPU_MAXIMUM_PROCESSORSSebastian Huber2016-03-041-0/+2
| | | | Maximum number of processors of all systems supported by this CPU port.
* score: Introduce CPU_CACHE_LINE_BYTESSebastian Huber2016-01-261-21/+2
| | | | | Add CPU_CACHE_LINE_BYTES for the maximum cache line size in bytes. The actual processor may use no cache or a smaller cache line size.
* score: Delete obsolete CPU_TIMESTAMP_* definesSebastian Huber2016-01-251-2/+0
| | | | Update #2271.
* powerpc: Fix alignment for AltiVec multilibsSebastian Huber2016-01-121-2/+6
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* powerpc: Add FSL cache definesSebastian Huber2015-10-281-0/+10
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* basedefs.h: Add and use RTEMS_NO_RETURNSebastian Huber2015-10-261-1/+1
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* powerpc: Use wrtee for e6500 multilibSebastian Huber2015-10-021-0/+17
| | | | This reduces the code size.
* powerpc: Do not use the ATB for e500 multilibSebastian Huber2015-07-151-1/+1
| | | | | | The e500v1 has no support for the ATB. Update #2369.
* powerpc: Fix _CPU_Counter_read()Nick Withers2015-07-151-1/+1
| | | | | | The mftb is not available on Book E processors. Use SPR 268 instead. Close #2369.
* powerpc: Add BUCSR register definesSebastian Huber2015-07-081-0/+2
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* cpukit: add and use CPU_Uint32ptr typeGedare Bloom2015-03-161-0/+4
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* score: Delete unused CPU_UNROLL_ENQUEUE_PRIORITYSebastian Huber2015-03-051-20/+0
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* score: Add _CPU_SMP_Prepare_start_multitasking()Sebastian Huber2015-02-171-0/+2
| | | | Update #2268.
* powerpc: Fix AltiVec VSCR save/restoreSebastian Huber2015-01-203-10/+13
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* powerpc: AltiVec and FPU context supportSebastian Huber2015-01-135-8/+700
| | | | | | | | | | | Add AltiVec and FPU support to the Context_Control in case we use the e6500 multilib. Add PPC_MULTILIB_ALTIVEC and PPC_MULTILIB_FPU multilib defines. Add non-volatile AltiVec and FPU context to Context_Control. Add save/restore of non-volatile AltiVec and FPU to _CPU_Context_switch(). Add save/restore of volatile AltiVec and FPU context to the exception code. Adjust data cache optimizations for the new context and cache line size.
* powerpc: Add AltiVec register ASM definesSebastian Huber2015-01-091-0/+32
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* powerpc: Use PPC_HAS_FPUSebastian Huber2015-01-091-0/+2
| | | | Provide floating point context support only if PPC_HAS_FPU == 1.
* powerpc: Add PPC_STACK_ALIGN_POWERSebastian Huber2015-01-091-16/+6
| | | | Simplify PPC_STACK_ALIGNMENT definition.
* powerpc: Set PPC_DEFAULT_CACHE_LINE_SIZE for e6500Sebastian Huber2015-01-092-6/+12
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* powerpc: Use PPC_DEFAULT_CACHE_LINE_SIZESebastian Huber2015-01-092-3/+4
| | | | | Use it for the default PPC_CACHE_ALIGNMENT. Use it for PPC_STRUCTURE_ALIGNMENT.
* powerpc: Delete _CPU_IRQ_infoSebastian Huber2015-01-091-16/+0
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* powerpc: Use alternate time base for CPU counterSebastian Huber2015-01-091-3/+3
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* powerpc: Use CPU_TIMESTAMP_USE_STRUCT_TIMESPECSebastian Huber2014-09-231-1/+1
| | | | | | | Converting 64-bit nanoseconds values into the common struct timeval or struct timespec formats requires a 64-bit division to get the seconds value. Performance analysis of high network loads revealed that this is too costly on PowerPC.
* score: Rename _BSP_Exception_frame_print()Sebastian Huber2014-09-111-8/+1
| | | | | Rename _BSP_Exception_frame_print() to _CPU_Exception_frame_print() to be in line with other CPU port functions.
* powerpc: Delete PPC_BSP_HAS_FIXED_PR288Sebastian Huber2014-09-111-7/+0
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* Let CPU/BSP Fatal handler have access to sourceDaniel Hellstrom2014-09-101-1/+1
| | | | | | | | | Without the source the error code does not say that much. Let it be up to the CPU/BSP to determine the error code reported on fatal shutdown. This patch does not change the current behaviour, just adds the option to handle the source of the fatal halt.
* Regenerate all preinstall.am files.Chris Johns2014-08-291-3/+3
| | | | | With this patch the preinstall.am files are in a set order and not dependent on now perl implements a hash.
* Regenerate all preinstall.am files.Joel Sherrill2014-08-281-3/+3
| | | | | Apparently, at some point automake output changed and these were not updated.
* score: PR2183: Fix context switch on SMPSebastian Huber2014-07-041-1/+1
| | | | | | | | Fix context switch on SMP for ARM, PowerPC and SPARC. Atomically test and set the is executing indicator of the heir context to ensure that at most one processor uses the heir context. Break the busy wait loop also due to heir updates.
* score: Fix CPU context usage on SMPSebastian Huber2014-05-081-2/+14
| | | | | | | | | | We must not alter the is executing indicator in _CPU_Context_Initialize() since this would cause an invalid state during a self restart. The is executing indicator must be valid at creation time since otherwise _Thread_Kill_zombies() uses an undefined value for not started threads. This could result in a system life lock.
* score: Implement forced thread migrationSebastian Huber2014-05-072-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current implementation of task migration in RTEMS has some implications with respect to the interrupt latency. It is crucial to preserve the system invariant that a task can execute on at most one processor in the system at a time. This is accomplished with a boolean indicator in the task context. The processor architecture specific low-level task context switch code will mark that a task context is no longer executing and waits that the heir context stopped execution before it restores the heir context and resumes execution of the heir task. So there is one point in time in which a processor is without a task. This is essential to avoid cyclic dependencies in case multiple tasks migrate at once. Otherwise some supervising entity is necessary to prevent life-locks. Such a global supervisor would lead to scalability problems so this approach is not used. Currently the thread dispatch is performed with interrupts disabled. So in case the heir task is currently executing on another processor then this prolongs the time of disabled interrupts since one processor has to wait for another processor to make progress. It is difficult to avoid this issue with the interrupt latency since interrupts normally store the context of the interrupted task on its stack. In case a task is marked as not executing we must not use its task stack to store such an interrupt context. We cannot use the heir stack before it stopped execution on another processor. So if we enable interrupts during this transition we have to provide an alternative task independent stack for this time frame. This issue needs further investigation.
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