| Commit message (Collapse) | Author | Age | Files | Lines |
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Fix context switch on SMP for ARM, PowerPC and SPARC.
Atomically test and set the is executing indicator of the heir context
to ensure that at most one processor uses the heir context. Break the
busy wait loop also due to heir updates.
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We must not alter the is executing indicator in
_CPU_Context_Initialize() since this would cause an invalid state during
a self restart.
The is executing indicator must be valid at creation time since
otherwise _Thread_Kill_zombies() uses an undefined value for not started
threads. This could result in a system life lock.
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The current implementation of task migration in RTEMS has some
implications with respect to the interrupt latency. It is crucial to
preserve the system invariant that a task can execute on at most one
processor in the system at a time. This is accomplished with a boolean
indicator in the task context. The processor architecture specific
low-level task context switch code will mark that a task context is no
longer executing and waits that the heir context stopped execution
before it restores the heir context and resumes execution of the heir
task. So there is one point in time in which a processor is without a
task. This is essential to avoid cyclic dependencies in case multiple
tasks migrate at once. Otherwise some supervising entity is necessary to
prevent life-locks. Such a global supervisor would lead to scalability
problems so this approach is not used. Currently the thread dispatch is
performed with interrupts disabled. So in case the heir task is
currently executing on another processor then this prolongs the time of
disabled interrupts since one processor has to wait for another
processor to make progress.
It is difficult to avoid this issue with the interrupt latency since
interrupts normally store the context of the interrupted task on its
stack. In case a task is marked as not executing we must not use its
task stack to store such an interrupt context. We cannot use the heir
stack before it stopped execution on another processor. So if we enable
interrupts during this transition we have to provide an alternative task
independent stack for this time frame. This issue needs further
investigation.
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Add and use _CPU_SMP_Start_processor(). Add and use
_CPU_SMP_Finalize_initialization(). This makes most
_CPU_SMP_Initialize() functions a bit simpler since we can calculate the
minimum value of the count of processors requested by the application
configuration and the count of physically or virtually available
processors in the high-level code.
The CPU port has now the ability to signal a processor start failure.
With the support for clustered/partitioned scheduling the presence of
particular processors can be configured to be optional or mandatory.
There will be a fatal error only in case mandatory processors are not
present.
The CPU port may use a timeout to monitor the start of a processor.
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Rename Priority_bit_map_Control in Priority_bit_map_Word.
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Remove RTEMS_COMPILER_PURE_ATTRIBUTE from _SMP_Get_current_processor()
and all _CPU_SMP_Get_current_processor(). Make inline ASM statements
volatile again. Test smptests/smpmigration01 showed that GCC optimizes
too much otherwise.
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Rename bsp_smp_initialize() into _CPU_SMP_Initialize() since every CPU
port must supply this function.
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Use a ticket lock implementation based on atomic operations. Delete CPU
port specific SMP lock implementations.
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The instructions to get the processor current index have no
side-effects.
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Add a CPU counter interface to allow access to a free-running counter.
It is useful to measure short time intervals. This can be used for
example to enable profiling of critical low-level functions.
Add two busy wait functions rtems_counter_delay_ticks() and
rtems_counter_delay_nanoseconds() implemented via the CPU counter.
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Delete _CPU_Context_switch_to_first_task_smp() and use
_CPU_Context_restore() instead.
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Tested and implemented on ARM, m68k, PowerPC and SPARC. Other
architectures need more work.
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The r2 may be used for thread-local storage.
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Add proper license and copyright.
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Add CPU port specific per-CPU control.
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Rename to _CPU_SMP_Processor_event_receive().
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Rename to _CPU_SMP_Processor_event_broadcast().
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Delete bsp_smp_interrupt_cpu().
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Add and use _SMP_Get_current_processor() and
rtems_smp_get_current_processor().
Delete bsp_smp_interrupt_cpu().
Change type of current processor index from int to uint32_t to match
_SMP_Processor_count type.
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Use the right context.
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Add CPU port type CPU_Exception_frame and function
_CPU_Exception_frame_print().
The CPU ports of avr, bfin, h8300, lm32, m32c, m32r, m68k, nios2, sh,
sparc64, and v850 use an empty default implementation of
_CPU_Exception_frame_print().
Add rtems_exception_frame and rtems_exception_frame_print().
Add RTEMS_FATAL_SOURCE_EXCEPTION for CPU exceptions. Use rtems_fatal()
with source RTEMS_FATAL_SOURCE_EXCEPTION in CPU ports of i386, powerpc,
and sparc for unexpected exceptions.
Add third parameter to RTEMS_BSP_CLEANUP_OPTIONS() which controls the
BSP_PRINT_EXCEPTION_CONTEXT define used in the default
bsp_fatal_extension().
Add test sptests/spfatal26.
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The powerpc port uses now a unified CPU_Exception_frame. This resulted
in a CPU_Exception_frame layout change for the MPC5XX.
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Add and use new CPU port define CPU_SIZEOF_POINTER. It must be an
integer literal that can be used by the assembler. This value will be
used to calculate offsets of structure members. These offsets will be
used in assembler code.
The size of a pointer is part of the application binary interface (ABI)
and thus independent of the actual programming language. The compiler
will provide defines to determine the current ABI. We use these defines
to select the appropriate CPU_SIZEOF_POINTER value.
Static assertions in the new file "cpukit/score/src/percpuasm.c" will
ensure that the value of CPU_SIZEOF_POINTER is consistent with the
current compiler settings. Also the offset values used by assembler
code are verfied.
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This function is only used if CPU_HAS_HARDWARE_INTERRUPT_STACK == TRUE.
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_CPU_ISR_Initialize
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PowerPC cores with the SPE (Signal Processing Extension) have 64-bit
general-purpose registers. The SPE context switch code has been merged
with the standard context switch code. The context switch may use cache
operations to increase the performance. It will be ensured that the
context is 32-byte aligned (PPC_DEFAULT_CACHE_LINE_SIZE). This
increases the overall memory size of the context area in the thread
control block slightly. The general-purpose registers GPR2 and GPR13
are no longer part of the context. The BSP must initialize these
registers during startup (usually initialized by the __eabi() function).
The new BSP option BSP_USE_DATA_CACHE_BLOCK_TOUCH can be used to enable
the dcbt instruction in the context switch.
The new BSP option BSP_USE_SYNC_IN_CONTEXT_SWITCH can be used to enable
sync and isync instructions in the context switch. This should be not
necessary in most cases.
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Script does what is expected and tries to do it as
smartly as possible.
+ remove occurrences of two blank comment lines
next to each other after Id string line removed.
+ remove entire comment blocks which only exited to
contain CVS Ids
+ If the processing left a blank line at the top of
a file, it was removed.
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In particular CPU_INTERRUPT_NUMBER_OF_VECTORS and
CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER are only used on
Simple Vectored Architectures, so do not depend on
them being defined. This disables as much as possible
that is specific to the Simple Vectored Model and
not expected to be used on architectures which use
the Programmable Interrupt Controller model for
interrupt handler vectoring.
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PR 1914/cpukit
* rtems/score/cpu.h: Select timestamp implementation.
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* rtems/score/cpu.h: Add more context access functionality. Needed to
get GDB debugger hooks working.
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* rtems/score/cpu.h: Added SPE support to CPU context.
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* rtems/powerpc/registers.h, rtems/score/cpu.h:
Use "__asm__" instead of "asm" for improved c99-compliance.
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* rtems/score/cpu.h: Add RTEMS_COMPILER_NO_RETURN_ATTRIBUTE to
_CPU_Context_restore() because it does not return. Telling GCC this
avoids generation of dead code.
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PR 1635/cpukit
* rtems/score/cpu.h, rtems/score/types.h: Refactoring of priority
handling, to isolate the bitmap implementation of priorities in the
supercore so that priority management is a little more modular. This
change is in anticipation of scheduler implementations that can
select how they manage tracking priority levels / finding the highest
priority ready task. Note that most of the changes here are simple
renaming, to clarify the use of the bitmap-based priority management.
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* rtems/new-exceptions/cpu.h: Removed file.
* Makefile.am, preinstall.am: Reflect change above.
* rtems/score/cpu.h: Include <rtems/score/types.h> first. Added
contents of <rtems/new-exceptions/cpu.h>.
* rtems/score/types.h: Use <rtems/score/basedefs.h> header file.
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* score/cpu/powerpc/rtems/score/cpu.h: Added space for non-
volatile AltiVec registers to context struct. Added declaration
for AltiVec-related routines to be implemented by CPU/BSP
support.
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* rtems/score/cpu.h: Changed fpscr field to an integer type in
Context_Control_fp. Fixed warnings in PPC_Set_timebase_register().
Changed _CPU_Context_Initialize_fp() to initialize all fields and
avoid floating-point instructions.
* rtems/score/powerpc.h: Removed PPC_INIT_FPSCR define.
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* rtems/new-exceptions/cpu.h, rtems/score/cpu.h: Eliminate
_CPU_Thread_dispatch_pointer and passing address of _Thread_Dispatch
to _CPU_Initialize. Clean up comments.
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* rtems/score/cpu.h: Move extern of bsp_clicks_per_usec so it is not
nested inside braces.
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