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* score: Introduce CPU_CACHE_LINE_BYTESSebastian Huber2016-01-261-25/+3
| | | | | Add CPU_CACHE_LINE_BYTES for the maximum cache line size in bytes. The actual processor may use no cache or a smaller cache line size.
* score: Delete obsolete CPU_TIMESTAMP_* definesSebastian Huber2016-01-251-2/+0
| | | | Update #2271.
* basedefs.h: Add and use RTEMS_NO_RETURNSebastian Huber2015-10-261-1/+1
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* score: Add Thread_Control::is_fpSebastian Huber2015-06-091-2/+10
| | | | | | | | Store the floating-point unit property in the thread control block regardless of the CPU_HARDWARE_FP and CPU_SOFTWARE_FP settings. Make sure the floating-point unit is only enabled for the corresponding multilibs. This helps targets which have a volatile only floating point context like SPARC for example.
* cpukit: add and use CPU_Uint32ptr typeGedare Bloom2015-03-161-0/+3
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* score: Delete unused CPU_UNROLL_ENQUEUE_PRIORITYSebastian Huber2015-03-051-20/+0
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* score: Rename _BSP_Exception_frame_print()Sebastian Huber2014-09-111-8/+1
| | | | | Rename _BSP_Exception_frame_print() to _CPU_Exception_frame_print() to be in line with other CPU port functions.
* Let CPU/BSP Fatal handler have access to sourceDaniel Hellstrom2014-09-101-1/+1
| | | | | | | | | Without the source the error code does not say that much. Let it be up to the CPU/BSP to determine the error code reported on fatal shutdown. This patch does not change the current behaviour, just adds the option to handle the source of the fatal halt.
* Regenerate all preinstall.am files.Chris Johns2014-08-291-3/+3
| | | | | With this patch the preinstall.am files are in a set order and not dependent on now perl implements a hash.
* Regenerate all preinstall.am files.Joel Sherrill2014-08-281-3/+3
| | | | | Apparently, at some point automake output changed and these were not updated.
* score: Statically initialize _ISR_Vector_tableSebastian Huber2014-04-292-10/+0
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* score: Rename Priority_bit_map_ControlSebastian Huber2014-04-032-2/+2
| | | | Rename Priority_bit_map_Control in Priority_bit_map_Word.
* Change all references of rtems.com to rtems.org.Chris Johns2014-03-216-6/+6
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* score: Add CPU counter supportSebastian Huber2014-02-142-0/+12
| | | | | | | | | Add a CPU counter interface to allow access to a free-running counter. It is useful to measure short time intervals. This can be used for example to enable profiling of critical low-level functions. Add two busy wait functions rtems_counter_delay_ticks() and rtems_counter_delay_nanoseconds() implemented via the CPU counter.
* Add thread-local storage (TLS) supportSebastian Huber2014-02-042-2/+4
| | | | | Tested and implemented on ARM, m68k, PowerPC and SPARC. Other architectures need more work.
* mips/.../cpu.h: Comment improvementJoel Sherrill2013-11-141-1/+3
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* score: Simplify <rtems/score/cpuatomic.h>WeiY2013-08-281-30/+6
| | | | Add proper license and copyright.
* score: Per-CPU thread dispatch disable levelSebastian Huber2013-08-091-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use a per-CPU thread dispatch disable level. So instead of one global thread dispatch disable level we have now one instance per processor. This is a major performance improvement for SMP. On non-SMP configurations this may simplifiy the interrupt entry/exit code. The giant lock is still present, but it is now decoupled from the thread dispatching in _Thread_Dispatch(), _Thread_Handler(), _Thread_Restart_self() and the interrupt entry/exit. Access to the giant lock is now available via _Giant_Acquire() and _Giant_Release(). The giant lock is still implicitly acquired via _Thread_Dispatch_decrement_disable_level(). The giant lock is only acquired for high-level operations in interrupt handlers (e.g. release of a semaphore, sending of an event). As a side-effect this change fixes the lost thread dispatch necessary indication bug in _Thread_Dispatch(). A per-CPU thread dispatch disable level greatly simplifies the SMP support for the interrupt entry/exit code since no spin locks have to be acquired in this area. It is only necessary to get the current processor index and use this to calculate the address of the own per-CPU control. This reduces the interrupt latency considerably. All elements for the interrupt entry/exit code are now part of the Per_CPU_Control structure: thread dispatch disable level, ISR nest level and thread dispatch necessary. Nothing else is required (except CPU port specific stuff like on SPARC).
* score/cpu: Add CPU_Per_CPU_controlSebastian Huber2013-08-091-0/+6
| | | | Add CPU port specific per-CPU control.
* update-all-architectures-to-new-atomic-implementationWeiY2013-07-171-6/+4
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* score: Add CPU context validationSebastian Huber2013-05-101-0/+12
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* Revert bootstrap whitespace changes.Chris Johns2013-05-101-0/+1
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* Using the generic atomic ops to implement UP mode atomic for all ↵WeiY2013-05-013-0/+44
| | | | architectures. SMP atomic port will be later.
* mips: Fix warningsSebastian Huber2013-04-231-0/+1
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* RTEMS: Delete ChangeLog files.Gedare Bloom2013-03-081-715/+0
| | | | | | | | | This commit deletes all RTEMS ChangeLog files. These files have been abandoned since converting to git version control. The historical data may be recovered by checking out any commit before this one. Most of the contents of these ChangeLog files can also be found in the git log. Two external ChangeLog files, ChangeLog.slac and ChangeLog.zlib, remain.
* cpukit: Add EOL on files missing EOL at EOFJoel Sherrill2013-01-105-5/+5
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* score: Doxygen Clean Up Task #4Alex Ivanov2013-01-081-9/+12
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* score: Doxygen Clean Up Task #3Mathew Kallada2013-01-045-73/+131
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* score misc: Score misc: Clean up Doxygen #9 (GCI 2012)Alex Ivanov2012-11-301-39/+7
| | | | | | | This patch is a task from GCI 2012 which improves the Doxygen comments in the RTEMS source. https://google-melange.appspot.com/gci/task/view/google/gci2012/7977211
* score: Add CPU_Exception_frameSebastian Huber2012-11-271-0/+13
| | | | | | | | | | | | | | | | | | | | | Add CPU port type CPU_Exception_frame and function _CPU_Exception_frame_print(). The CPU ports of avr, bfin, h8300, lm32, m32c, m32r, m68k, nios2, sh, sparc64, and v850 use an empty default implementation of _CPU_Exception_frame_print(). Add rtems_exception_frame and rtems_exception_frame_print(). Add RTEMS_FATAL_SOURCE_EXCEPTION for CPU exceptions. Use rtems_fatal() with source RTEMS_FATAL_SOURCE_EXCEPTION in CPU ports of i386, powerpc, and sparc for unexpected exceptions. Add third parameter to RTEMS_BSP_CLEANUP_OPTIONS() which controls the BSP_PRINT_EXCEPTION_CONTEXT define used in the default bsp_fatal_extension(). Add test sptests/spfatal26.
* score: PR1607: Add and use CPU_SIZEOF_POINTERSebastian Huber2012-11-221-0/+2
| | | | | | | | | | | | | | | | | Add and use new CPU port define CPU_SIZEOF_POINTER. It must be an integer literal that can be used by the assembler. This value will be used to calculate offsets of structure members. These offsets will be used in assembler code. The size of a pointer is part of the application binary interface (ABI) and thus independent of the actual programming language. The compiler will provide defines to determine the current ABI. We use these defines to select the appropriate CPU_SIZEOF_POINTER value. Static assertions in the new file "cpukit/score/src/percpuasm.c" will ensure that the value of CPU_SIZEOF_POINTER is consistent with the current compiler settings. Also the offset values used by assembler code are verfied.
* mips/idtcpu.h: Fix nested comment warningJoel Sherrill2012-09-051-1/+1
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* mips/cpu.h: Define CPU_SIMPLE_VECTORED_INTERRUPTS and remove _CPU_ISR_InitializeJoel Sherrill2012-06-111-7/+2
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* Remove All CVS Id Strings Possible Using a ScriptJoel Sherrill2012-05-119-20/+0
| | | | | | | | | | | | Script does what is expected and tries to do it as smartly as possible. + remove occurrences of two blank comment lines next to each other after Id string line removed. + remove entire comment blocks which only exited to contain CVS Ids + If the processing left a blank line at the top of a file, it was removed.
* Revert: Remove CVS IdsJoel Sherrill2012-05-071-0/+4
| | | | | See http://www.rtems.org/pipermail/rtems-devel/2012-May/001006.html for details.
* Remove CVS-Ids.Ralf Corsépius2012-05-041-4/+0
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* PR 1993 - Convert MIPS to PIC IRQ modelJennifer Averett2012-04-043-77/+34
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* Remove all .cvsignore files.Joel Sherrill2012-02-011-2/+0
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* 2011-12-09 Jennifer AverettJennifer Averett2011-12-092-1/+5
| | | | * cpu.c: Correct typo.
* 2011-09-27 Sebastian Huber <sebastian.huber@embedded-brains.de>Sebastian Huber2011-09-272-0/+7
| | | | | PR 1914/cpukit * rtems/score/cpu.h: Select timestamp implementation.
* 2011-07-24 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill2011-07-242-10/+10
| | | | | * cpu.c: Remove /*PAGE markers which were interpreted by a long dead print script.
* 2011-05-17 Ralf Corsépius <ralf.corsepius@rtems.org>Ralf Corsepius2011-05-172-3/+9
| | | | * Makefile.am: Reformat.
* 2011-02-11 Ralf Corsépius <ralf.corsepius@rtems.org>Ralf Corsepius2011-02-113-17/+22
| | | | | * cpu.c, rtems/score/mips.h: Use "__asm__" instead of "asm" for improved c99-compliance.
* 2011-01-04 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill2011-01-042-1/+4
| | | | * cpu_asm.S: _Thread_Executing was not used.
* 2010-10-21 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill2010-10-212-1/+7
| | | | | | * rtems/score/cpu.h: Add RTEMS_COMPILER_NO_RETURN_ATTRIBUTE to _CPU_Context_restore() because it does not return. Telling GCC this avoids generation of dead code.
* 2010-07-30 Gedare Bloom <giddyup44@yahoo.com>Joel Sherrill2010-07-302-1/+7
| | | | | | PR 1599/cpukit * cpu_asm.S: Rename _Context_Switch_necessary to _Thread_Dispatch_necessary to more properly reflect the intent.
* 2010-07-29 Gedare Bloom <giddyup44@yahoo.com>Joel Sherrill2010-07-293-2/+13
| | | | | | | | | | | PR 1635/cpukit * rtems/score/cpu.h, rtems/score/types.h: Refactoring of priority handling, to isolate the bitmap implementation of priorities in the supercore so that priority management is a little more modular. This change is in anticipation of scheduler implementations that can select how they manage tracking priority levels / finding the highest priority ready task. Note that most of the changes here are simple renaming, to clarify the use of the bitmap-based priority management.
* 2010-07-16 Sebastian Huber <sebastian.huber@embedded-brains.de>Sebastian Huber2010-07-163-20/+8
| | | | | * rtems/score/cpu.h: Include <rtems/score/types.h> first. * rtems/score/types.h: Use <rtems/score/basedefs.h> header file.
* 2010-07-01 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill2010-07-013-1/+9
| | | | | | | * rtems/asm.h, rtems/score/cpu.h: cpu.h defines were not available to assembly programs. This resulted in percpu.h (when included from assembly) not being able to detect that the MIPS does not have a dedicated software managed interrupt stack.
* 2010-06-28 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill2010-06-293-45/+20
| | | | | | | | PR 1573/cpukit * cpu_asm.S, rtems/score/cpu.h: Add a per cpu data structure which contains the information required by RTEMS for each CPU core. This encapsulates information such as thread executing, heir, idle and dispatch needed.
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