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A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.
This has at least seven problems:
* The make preinstall step itself needs time and disk space.
* Errors in header files show up in the build tree copy. This makes it
hard for editors to open the right file to fix the error.
* There is no clear relationship between source and build tree header
files. This makes an audit of the build process difficult.
* The visibility of all header files in the build tree makes it
difficult to enforce API barriers. For example it is discouraged to
use BSP-specifics in the cpukit.
* An introduction of a new build system is difficult.
* Include paths specified by the -B option are system headers. This
may suppress warnings.
* The parallel build had sporadic failures on some hosts.
This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.
The new cpukit include directories are:
* cpukit/include
* cpukit/score/cpu/@RTEMS_CPU@/include
* cpukit/libnetworking
The new BSP include directories are:
* bsps/include
* bsps/@RTEMS_CPU@/include
* bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include
There are build tree include directories for generated files.
The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.
The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.
Update #3254.
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Script does what is expected and tries to do it as
smartly as possible.
+ remove occurrences of two blank comment lines
next to each other after Id string line removed.
+ remove entire comment blocks which only exited to
contain CVS Ids
+ If the processing left a blank line at the top of
a file, it was removed.
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* rtems/mips/idtcpu.h, rtems/mips/iregdef.h, rtems/score/mips.h:
Header guards cleanup.
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* cpu_asm.S: Collected PR 601 changes for commit to cvshead
for rtems-4.7
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* cpu_asm.S: Fixed exception return address, modified FP context
switch so FPU is properly enabled and also doesn't screw up the
exception FP handling.
* idtcpu.h: Added C0_TAR, the MIPS target address register used for
returning from exceptions.
* iregdef.h: Added R_TAR to the stack frame so the target address
can be saved on a per-exception basis. The new entry is past the
end of the frame gdb cares about, so doesn't affect gdb or cpu.h
stuff.
* rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
to obtain FPU defines without systax errors generated by the C
defintions.
* cpu.c: Improved interrupt level saves & restores.
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* iregdef.h, rtems/score/cpu.h: Reordered register in the
exception stack frame to better match gdb's expectations.
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* cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
Also reimplemented some assembly routines in C further reducing
the amount of assembly and increasing maintainability.
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* cpu_asm.h: Removed.
* Makefile.am: Remove cpu_asm.h.
* rtems/score/mips64orion.h: Renamed mips.h.
* rtems/score/mips.h: New file, formerly mips64orion.h.
Header rewritten.
(mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
mips_disable_in_interrupt_mask): New macros.
* rtems/score/Makefile.am: Reflect renaming mips64orion.h.
* asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
few defines that were in <cpu_asm.h>.
* cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
MIPS ISA 3 is still in assembly for now.
(_CPU_Thread_Idle_body): Rewrote in C.
* cpu_asm.S: Rewrote file header.
(FRAME,ENDFRAME) now in asm.h.
(_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
(_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
(_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
leaves other bits in SR alone on task switch.
(mips_enable_interrupts,mips_disable_interrupts,
mips_enable_global_interrupts,mips_disable_global_interrupts,
disable_int, enable_int): Removed.
(mips_get_sr): Rewritten as C macro.
(_CPU_Thread_Idle_body): Rewritten in C.
(init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
placed in libcpu.
(exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
to libcpu/mips/shared/interrupts.
(general): Cleaned up comment blocks and #if 0 areas.
* idtcpu.h: Made ifdef report an error.
* iregdef.h: Removed warning.
* rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
number defined by libcpu.
(_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
to access SR.
(_CPU_ISR_Set_level): Rewritten as macro for ISA I.
(_CPU_Context_Initialize): Honor ISR level in task initialization.
(_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
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Joel Sherrill <joel@OARcorp.com>
* This is a major reworking of the mips64orion port to use
gcc predefines as much as possible and a big push to multilib
the mips port. The mips64orion port was copied/renamed to mips
to be more like other GNU tools. Alan did most of the technical
work of determining how to map old macro names used by the mips64orion
port to standard compiler macro definitions. Joel did the merge
with CVS magic to keep individual file history and did the BSP
modifications. Details follow:
* Makefile.am: idtmon.h in mips64orion port not present.
* asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
* cpu.c: Comments added.
* cpu_asm.S: Conditionals changed. MIPS ISA level 1 support added.
First attempt at exception/interrupt processing for ISA level 1
and minus any use of IDT/MON added.
* idtcpu.h: Conditionals changed to use gcc predefines.
* iregdef.h: Ditto.
* cpu_asm.h: No real change. Merger required commit.
* rtems/Makefile.am: Ditto.
* rtems/score/Makefile.am: Ditto.
* rtems/score/cpu.h: Change MIPS64ORION to MIPS.
* rtems/score/mips64orion.h: Change MIPS64ORION to MIPS. Convert
from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
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> 4) rtems-rc-19990202-0.diff /reorg-score-cpu.sh
>
> reorg-score-cpu.sh reorganizes the cpu/<cpu>/* subdirectories in a
> similar manner than previous reorg scripts did. rtems-rc-19990202-0.diff
> contains the diffs after reorg-score-cpu.sh has been run on a
> rtems-19981215 snapshot + my patches up to rtems-rc-19990131-2.diff.
>
> This patch is rather nasty and may break something. However, I've tested
> it for about 10 different target/bsp pairs and believe to have shaken
> out most bugs.
I wonder about the following .h files that were not moved:
a29k/asm.h
a29k/cpu_asm.h
i386/asm.h
i960/asm.h
m68k/asm.h
m68k/m68302.h
m68k/m68360.h
m68k/qsm.h
m68k/sim.h
mips64orion/asm.h
mips64orion/cpu_asm.h
mips64orion/mips64orion.h
no_cpu/asm.h
no_cpu/cpu_asm.h
powerpc/asm.h
powerpc/mpc860.h
sh/asm.h
sparc/asm.h
sparc/erc32.h
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