| Commit message (Collapse) | Author | Age | Files | Lines |
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* cpu.c, cpu_asm.S, rtems/score/cpu.h, rtems/score/m68k.h,
rtems/score/types.h: URL for license changed.
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* cpu_asm.S: Per PR267, the _ISR_Handler() function never was modifying
_ISR_Nest_level, and _Watchdog_Insert() requires this variable
to be modified to determine if an interrupt may have modified
the watchdog chain. Prior to modifying _ISR_Handler(), I had
a test that would fail if _ISR_Flash was not commented out in
_Watchdog_Insert(). After this modification was made, my test
ran flawlessly.
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* rtems/score/m68k.h: Per PR227, mc68060 does not require FPSP
since it is now multilib'ed.
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* Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
* include/rtems/score/ispsh7750.h, score/ispsh7750.c: Account for
name change.
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* rtems/score/m68k.h: m68k_swap_u32 fix typo.
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* rtems/score/m68k.h [M68K_COLDFIRE_ARCH] (CPU_swap_u16, CPU_swap_u32):
Generic implementation of endian swap primitives added for Coldfire
family.
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This was tracked as PR91.
* rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
is used to specify if the port uses the standard macro for this (FALSE).
A TRUE setting indicates the port provides its own implementation.
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* rtems/score/cpu.h: Added _CPU_Initialize_vectors().
* cpu_asm.S: Modify to properly dereference _ISR_Vector_table
now that it is dynamically allocated.
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* rtems/score/cpu.h: define CPU_Exception_frame for rdbg.
* m68302.h: Make buffer pointer in m302_SCC_bd volatile.
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now is an implementation of the prototypes in rtems/rtems/cache.h.
The libcpu/i386/wrapup directory is no longer needed.
The PowerPC needs this done to it.
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<charles.gauthier@iit.nrc.ca>, and Darlene A. Stewart
<Darlene.Stewart@nrc.ca> to add support for a number of very
significant things:
+ BSPs for many variations on the Motorola MBX8xx board series
+ Cache Manager including initial support for m68040
and PowerPC
+ Rework of mpc8xx libcpu code so all mpc8xx CPUs now use
same code base.
+ Rework of eth_comm BSP to utiltize above.
John reports this works on the 821 and 860
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adds .cvsignore.
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use correct ifdef conditional (__GNUC__ not __GCC__).
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unnecessarily uses any variables defined by the BSP. On this
sweep, use of BSP_Configuration and Cpu_table was eliminated.
A significant part of this modification was the addition of
macros to access fields in the RTEMS configuration structures.
This is necessary to strengthen the division between the BSP independent
parts of RTEMS and the BSPs themselves. This started after
comments and analysis by Ralf Corsepius <corsepiu@faw.uni-ulm.de>.
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to correct a typo CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES was actually
typed in as CPU_CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES.
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> 4) rtems-rc-19990202-0.diff /reorg-score-cpu.sh
>
> reorg-score-cpu.sh reorganizes the cpu/<cpu>/* subdirectories in a
> similar manner than previous reorg scripts did. rtems-rc-19990202-0.diff
> contains the diffs after reorg-score-cpu.sh has been run on a
> rtems-19981215 snapshot + my patches up to rtems-rc-19990131-2.diff.
>
> This patch is rather nasty and may break something. However, I've tested
> it for about 10 different target/bsp pairs and believe to have shaken
> out most bugs.
I wonder about the following .h files that were not moved:
a29k/asm.h
a29k/cpu_asm.h
i386/asm.h
i960/asm.h
m68k/asm.h
m68k/m68302.h
m68k/m68360.h
m68k/qsm.h
m68k/sim.h
mips64orion/asm.h
mips64orion/cpu_asm.h
mips64orion/mips64orion.h
no_cpu/asm.h
no_cpu/cpu_asm.h
powerpc/asm.h
powerpc/mpc860.h
sh/asm.h
sparc/asm.h
sparc/erc32.h
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