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Updates #3053.
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This function was only used on some m68k variants. On these m68k
variants there is no need to use a global symbol. Use a local label
instead.
Remove _ISR_Dispatch() from the architecture-independent layer.
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Statically initialize the interrupt stack area
(_Configuration_Interrupt_stack_area_begin,
_Configuration_Interrupt_stack_area_end, and
_Configuration_Interrupt_stack_size) via <rtems/confdefs.h>. Place the
interrupt stack area in a special section ".rtemsstack.interrupt". Let
BSPs define the optimal placement of this section in their linker
command files (e.g. in a fast on-chip memory).
This change makes makes the CPU_HAS_SOFTWARE_INTERRUPT_STACK and
CPU_HAS_HARDWARE_INTERRUPT_STACK CPU port defines superfluous, since the
low level initialization code has all information available via global
symbols.
This change makes the CPU_ALLOCATE_INTERRUPT_STACK CPU port define
superfluous, since the interrupt stacks are allocated by confdefs.h for
all architectures. There is no need for BSP-specific linker command
file magic (except the section placement), see previous ARM linker
command file as a bad example.
Remove _CPU_Install_interrupt_stack(). Initialize the hardware
interrupt stack in _CPU_Initialize() if necessary (e.g.
m68k_install_interrupt_stack()).
The optional _CPU_Interrupt_stack_setup() is still useful to customize
the registration of the interrupt stack area in the per-CPU information.
The initialization stack can reuse the interrupt stack, since
* interrupts are disabled during the sequential system initialization,
and
* the boot_card() function does not return.
This stack resuse saves memory.
Changes per architecture:
arm:
* Mostly replace the linker symbol based configuration of stacks with
the standard <rtems/confdefs.h> configuration via
CONFIGURE_INTERRUPT_STACK_SIZE. The size of the FIQ, ABT and UND
mode stack is still defined via linker symbols. These modes are
rarely used in applications and the default values provided by the
BSP should be sufficient in most cases.
* Remove the bsp_processor_count linker symbol hack used for the SMP
support. This is possible since the interrupt stack area is now
allocated by the linker and not allocated from the heap. This makes
some configure.ac stuff obsolete. Remove the now superfluous BSP
variants altcycv_devkit_smp and realview_pbx_a9_qemu_smp.
bfin:
* Remove unused magic linker command file allocation of initialization
stack. Maybe a previous linker command file copy and paste problem?
In the start.S the initialization stack is set to a hard coded value.
lm32, m32c, mips, nios2, riscv, sh, v850:
* Remove magic linker command file allocation of initialization stack.
Reuse interrupt stack for initialization stack.
m68k:
* Remove magic linker command file allocation of initialization stack.
Reuse interrupt stack for initialization stack.
powerpc:
* Remove magic linker command file allocation of initialization stack.
Reuse interrupt stack for initialization stack.
* Used dedicated memory region (REGION_RTEMSSTACK) for the interrupt
stack on BSPs using the shared linkcmds.base (replacement for
REGION_RWEXTRA).
sparc:
* Remove the hard coded initialization stack. Use the interrupt stack
for the initialization stack on the boot processor. This saves
16KiB of RAM.
Update #3459.
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Use a per-CPU thread dispatch disable level. So instead of one global
thread dispatch disable level we have now one instance per processor.
This is a major performance improvement for SMP. On non-SMP
configurations this may simplifiy the interrupt entry/exit code.
The giant lock is still present, but it is now decoupled from the thread
dispatching in _Thread_Dispatch(), _Thread_Handler(),
_Thread_Restart_self() and the interrupt entry/exit. Access to the
giant lock is now available via _Giant_Acquire() and _Giant_Release().
The giant lock is still implicitly acquired via
_Thread_Dispatch_decrement_disable_level().
The giant lock is only acquired for high-level operations in interrupt
handlers (e.g. release of a semaphore, sending of an event).
As a side-effect this change fixes the lost thread dispatch necessary
indication bug in _Thread_Dispatch().
A per-CPU thread dispatch disable level greatly simplifies the SMP
support for the interrupt entry/exit code since no spin locks have to be
acquired in this area. It is only necessary to get the current
processor index and use this to calculate the address of the own per-CPU
control. This reduces the interrupt latency considerably.
All elements for the interrupt entry/exit code are now part of the
Per_CPU_Control structure: thread dispatch disable level, ISR nest level
and thread dispatch necessary. Nothing else is required (except CPU
port specific stuff like on SPARC).
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Script does what is expected and tries to do it as
smartly as possible.
+ remove occurrences of two blank comment lines
next to each other after Id string line removed.
+ remove entire comment blocks which only exited to
contain CVS Ids
+ If the processing left a blank line at the top of
a file, it was removed.
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* cpu.c, cpu_asm.S: Remove /*PAGE markers which were interpreted by a
long dead print script.
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PR 1573/cpukit
* cpu_asm.S, rtems/score/cpu.h: Add a per cpu data structure which
contains the information required by RTEMS for each CPU core. This
encapsulates information such as thread executing, heir, idle and
dispatch needed.
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* cpu_asm.S, rtems/score/cpu.h: On uC5282, the thread restart needed to
reload the frame pointer. As part of doing this, the code was moved
from inline asm to the .S file.
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* cpu.c, cpu_asm.S: Add include of config.h
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initialization, save and restore code.
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PR 1385/cpukit
* cpu_asm.S: When the type rtems_boolean was switched to the C99 bool,
the size changed from 4 bytes to 1 byte. The interrupt dispatching
code accesses two boolean variables for scheduling purposes and the
assembly implementations of this code did not get updated.
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* cpu_asm.S: Add Coldfire FPU support.
* rtems/score/m68k.h: Change the Coldfire CPU defines to be based
on the instruction set. Add Tiny RTEMS support to the small memory
model RTEMS processors.
* rtems/score/cpu.h: Handle the new Tiny RTEMS support.
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* cpu_asm.S: Spacing and comment alignment.
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* cpu_asm.S: Reduce mask from 0xffc to 0x3fc so only the vector
bits are used when calculating the exception vector.
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* cpu_asm.S: Include <rtems/asm.h> instead of <asm.h>.
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* cpu.c, cpu_asm.S, rtems/score/cpu.h, rtems/score/m68k.h,
rtems/score/types.h: URL for license changed.
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* cpu_asm.S: More PR267 tinkering which eliminates some conditional
compilation.
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* cpu_asm.S: Per PR267, the _ISR_Handler() function never was modifying
_ISR_Nest_level, and _Watchdog_Insert() requires this variable
to be modified to determine if an interrupt may have modified
the watchdog chain. Prior to modifying _ISR_Handler(), I had
a test that would fail if _ISR_Flash was not commented out in
_Watchdog_Insert(). After this modification was made, my test
ran flawlessly.
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* cpu_asm.S: This patch was co-developed with Eric Norum
<eric.norum@usask.ca>. It closes a one instruction window
on some m68k CPU cores. It fixes symptoms seen as:
1) No more `interrupt handler invoked twice for
a single interrupt'.
2) No more `lockup when mc68360 CPM and PIT interrupts
are at different levels'.
It does insert a little more overhead on machines without hardware
interrupt stacks but correctness has a price.
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* rtems/score/cpu.h: Added _CPU_Initialize_vectors().
* cpu_asm.S: Modify to properly dereference _ISR_Vector_table
now that it is dynamically allocated.
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.s files to .S in conformance with GNU conventions. This is a
minor step along the way to supporting automake.
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Thanks to Rod Barman for this one.
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I found that my 68040/68360 test programs would not run even after
I fixed the `wrong BSP' problem.
It seems that there's a bug in the interrupt handling code for
processors with hardware interrupt stacks (e.g. 68040). The wrong
status register was getting pushed on the stack for the `return
from exception' to call _ISR__Dispatch. This ended up making
the context switch code run on the interrupt stack, so interrupt-driven
context switches would always fail.
I guess that no one has tried running any of the RTEMS-4.0 snapshots
on a 68040 machine!
Anyhow, here are the patches for
1) gen68360.cfg --- to fix the `wrong-BSP' problem.
2) m68k/cpu_asm.s --- to fix the hardware interrupt stack problem.
With these patches in place, the network demo programs run on my
68040/68360 system. The paranoia program runs with no failures,
defects nor flaws.
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Actual patch was from Eric Norum.
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which have hardware support for a separate interrupt stack.
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exiting from an ISR. This allows the trace bit to be set on a per task
basis and tracing to be limited to that task.
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software floating point emulation code. Code implemented by
Karen Sara Looney <Karen.Looney@colorado.edu> with much
email assistance from Joel.
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of switching to the modified GNU GPL.
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cores.
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68000 class CPUs.
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<jsg@coulomb.eng.ohio-state.edu> of the rest of the 68000-ish support
for interrupt handling and bfffo support, the two BSPs he submitted
(efi68k and efi332), and SGI Irix 5.3 host support.
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