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This was tracked as PR91.
* rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
is used to specify if the port uses the standard macro for this (FALSE).
A TRUE setting indicates the port provides its own implementation.
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* rtems/score/cpu.h: Added _CPU_Initialize_vectors().
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* rtems/score/c4x.h: Modified to properly multilib. This required
using only macros predefined by gcc.
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a BSP (c4xsim) supporting the simulator included with gdb. This port
was done by Joel Sherrill and Jennifer Averett of OAR Corporation.
Also included with this port is a space/time optimization to eliminate
FP context switch management on CPUs without hardware or software FP.
An issue with this port was that sizeof(unsigned32) = sizeof(unsigned8)
on this CPU. This required addressing alignment checks and assumptions
as well as fixing code that assumed sizeof(unsigned32) == 4.
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linkcmds updated, simio references removed, and switch to libchip for
serial ports from simio.
Added a MEMORY_MAP file to capture information about the various
addresses on this board.
In addition, many of the beta patches are now included.
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