| Commit message (Collapse) | Author | Age | Files | Lines |
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Use de-facto standard BYTE_ORDER instead.
Close #2803.
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On SMP configurations, it is a fatal error to call blocking operating
system with interrupts disabled, since this prevents delivery of
inter-processor interrupts. This could lead to executing threads which
are not allowed to execute resulting in undefined behaviour.
The ARM Cortex-M port has a similar problem, since the interrupt state
is not a part of the thread context.
Update #2811.
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Close #2817.
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In contrast to _ISR_Get_level() the _ISR_Is_enabled() function evaluates
a level parameter and returns a boolean value.
Update #2811.
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Update #2808.
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Move CPU_PER_CPU_CONTROL_SIZE and the optional CPU_Per_CPU_control to
<rtems/score/cpuimpl.h> to hide it from <rtems.h>.
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The thread dispatch inline option is no longer used.
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The aim of this file is to encapsulate CPU port implementation details.
This helps to hide implementation details from <rtems.h> which
indirectly includes <rtems/score/cpu.h>.
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Only use CPU_Per_CPU_control if it contains at least one filed. In GNU
C empty structures have a size of zero. In C++ structures have a
non-zero size. In case CPU_PER_CPU_CONTROL_SIZE is defined to zero,
then this structure is not used anymore.
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The priority bit map can deal with a maximum of 256 priority values
ranging from 0 to 255. Consistently use an unsigned int for
computation, due to the usual integer promotion rules.
Make Priority_bit_map_Word definition architecture-independent and
define it to uint16_t. This was already the case for all architectures
except PowerPC. Adjust the PowerPC bitmap support accordingly.
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Rename __log2table into _Bitfield_Leading_zeros since it acually returns
the count of leading zeros of an 8-bit integer. The value for zero is a
bit odd. Provide it unconditionally.
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Maximum number of processors of all systems supported by this CPU port.
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Update #2559.
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Add CPU_CACHE_LINE_BYTES for the maximum cache line size in bytes. The
actual processor may use no cache or a smaller cache line size.
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Update #2271.
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Closes #2148
Fix suggested in above ticket. On examination, the assembly
appears to be clearing the DISPATCH_NEEDED flag before jumping
to _Thread_Dispatch.
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Without the source the error code does not say that much.
Let it be up to the CPU/BSP to determine the error code
reported on fatal shutdown.
This patch does not change the current behaviour, just
adds the option to handle the source of the fatal halt.
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With this patch the preinstall.am files are in a set order and not
dependent on now perl implements a hash.
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Apparently, at some point automake output changed and these were
not updated.
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Rename Priority_bit_map_Control in Priority_bit_map_Word.
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Add a CPU counter interface to allow access to a free-running counter.
It is useful to measure short time intervals. This can be used for
example to enable profiling of critical low-level functions.
Add two busy wait functions rtems_counter_delay_ticks() and
rtems_counter_delay_nanoseconds() implemented via the CPU counter.
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Tested and implemented on ARM, m68k, PowerPC and SPARC. Other
architectures need more work.
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Add proper license and copyright.
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Use a per-CPU thread dispatch disable level. So instead of one global
thread dispatch disable level we have now one instance per processor.
This is a major performance improvement for SMP. On non-SMP
configurations this may simplifiy the interrupt entry/exit code.
The giant lock is still present, but it is now decoupled from the thread
dispatching in _Thread_Dispatch(), _Thread_Handler(),
_Thread_Restart_self() and the interrupt entry/exit. Access to the
giant lock is now available via _Giant_Acquire() and _Giant_Release().
The giant lock is still implicitly acquired via
_Thread_Dispatch_decrement_disable_level().
The giant lock is only acquired for high-level operations in interrupt
handlers (e.g. release of a semaphore, sending of an event).
As a side-effect this change fixes the lost thread dispatch necessary
indication bug in _Thread_Dispatch().
A per-CPU thread dispatch disable level greatly simplifies the SMP
support for the interrupt entry/exit code since no spin locks have to be
acquired in this area. It is only necessary to get the current
processor index and use this to calculate the address of the own per-CPU
control. This reduces the interrupt latency considerably.
All elements for the interrupt entry/exit code are now part of the
Per_CPU_Control structure: thread dispatch disable level, ISR nest level
and thread dispatch necessary. Nothing else is required (except CPU
port specific stuff like on SPARC).
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Add CPU port specific per-CPU control.
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architectures. SMP atomic port will be later.
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This commit deletes all RTEMS ChangeLog files. These files have been abandoned
since converting to git version control. The historical data may be recovered
by checking out any commit before this one. Most of the contents of these
ChangeLog files can also be found in the git log.
Two external ChangeLog files, ChangeLog.slac and ChangeLog.zlib, remain.
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This is the result of a sed script which converts all uses
of @{ into a consistent form.
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This patch is a task from GCI 2012 which improves the Doxygen
comments in the RTEMS source.
http://www.google-melange.com/gci/task/view/google/gci2012/8013205
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Add CPU port type CPU_Exception_frame and function
_CPU_Exception_frame_print().
The CPU ports of avr, bfin, h8300, lm32, m32c, m32r, m68k, nios2, sh,
sparc64, and v850 use an empty default implementation of
_CPU_Exception_frame_print().
Add rtems_exception_frame and rtems_exception_frame_print().
Add RTEMS_FATAL_SOURCE_EXCEPTION for CPU exceptions. Use rtems_fatal()
with source RTEMS_FATAL_SOURCE_EXCEPTION in CPU ports of i386, powerpc,
and sparc for unexpected exceptions.
Add third parameter to RTEMS_BSP_CLEANUP_OPTIONS() which controls the
BSP_PRINT_EXCEPTION_CONTEXT define used in the default
bsp_fatal_extension().
Add test sptests/spfatal26.
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Add and use new CPU port define CPU_SIZEOF_POINTER. It must be an
integer literal that can be used by the assembler. This value will be
used to calculate offsets of structure members. These offsets will be
used in assembler code.
The size of a pointer is part of the application binary interface (ABI)
and thus independent of the actual programming language. The compiler
will provide defines to determine the current ABI. We use these defines
to select the appropriate CPU_SIZEOF_POINTER value.
Static assertions in the new file "cpukit/score/src/percpuasm.c" will
ensure that the value of CPU_SIZEOF_POINTER is consistent with the
current compiler settings. Also the offset values used by assembler
code are verfied.
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Script does what is expected and tries to do it as
smartly as possible.
+ remove occurrences of two blank comment lines
next to each other after Id string line removed.
+ remove entire comment blocks which only exited to
contain CVS Ids
+ If the processing left a blank line at the top of
a file, it was removed.
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See http://www.rtems.org/pipermail/rtems-devel/2012-May/001006.html
for details.
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PR 1914/cpukit
* rtems/score/cpu.h: Select timestamp implementation.
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* cpu.c: Remove /*PAGE markers which were interpreted by a long dead
print script.
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* Makefile.am: Reformat.
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