| Commit message (Collapse) | Author | Files | Lines |
|---|
|
Enumerators are restricted to signed integers in some C standards.
|
|
Add _CPU_Get_TLS_thread_pointer() to get the thread pointer which is
used to get the address of thread-local storage objects associated with
a thread.
Update #4920.
|
|
Sponsored-By: Precidata
|
|
All CPU ports used the same <rtems/score/cpustdatomic.h> header file to
provide the atomic operations. Remove the header file indirection.
|
|
|
|
The embedded brains GmbH & Co. KG is the legal successor of embedded
brains GmbH.
|
|
Due to API change, the patch also fixes affected BSPs and uses
value provided by MPU CTRL spec option there.
Sponsored-By: Precidata
|
|
Close #4759.
|
|
Update #3835.
|
|
Directly use "static inline" which is available in C99 and later. This brings
the RTEMS implementation closer to standard C.
Close #3935.
|
|
All CPU ports used the same _CPU_Counter_difference() implementation. Remove
this CPU port interface and mandate a monotonically increasing CPU counter.
Close #3456.
|
|
At some point during system initialization, the idle threads are created.
Afterwards, the boot processor basically executes within the context of an idle
thread with thread dispatching disabled. On some architectures, the
thread-local storage area of the associated thread must be set in dedicated
processor registers. Add the new CPU port function to do this:
void _CPU_Use_thread_local_storage( const Context_Control *context )
Close #4672.
|
|
This simplifies unit testing.
|
|
Updates #4625.
|
|
The previous SMP multitasking start assumed that the initial heir thread of a
processor starts execution in _Thread_Handler(). The _Thread_Handler() sets
the interrupt state explicitly by _ISR_Set_level() before it calls the thread
entry. Under certain timing conditions, processors may perform an initial
context switch to a thread which already executes its thread body (see
smptests/smpstart01). In this case, interrupts are disabled after the context
switch on targets which do not save/restore the interrupt state during a
context switch (aarch64, arm, and riscv).
Close #4627.
|
|
Updates #3053.
|
|
Use the SRS (Store Return State) instruction if available. This
considerably simplifies the context save and restore.
|
|
Add default memory attributes for read-write data. The actual
attributes depend on the RTEMS_SMP build option.
Update #4202.
|
|
Fix definition of AARCH32_PMSA_DATA_READ_WRITE_CACHED. Since
AARCH32_PMSA_ATTR_AP_EL1_RW_EL0_NO is zero, this fix is only cosmetic.
Update #4202.
|
|
These two OAR copyright headers are the only two in the codebase with
a format that differs from the typical OAR copyright header. This makes
all of the OAR copyright headers consistent.
|
|
Move _CPU_Fatal_halt() declaration to <rtems/score/cpuimpl.h> and make sure it
is a proper declaration of a function which does not return. Fix the type of
the error code. If necessary, add the implementation to cpu.c. Implementing
_CPU_Fatal_halt() as a function makes it possible to wrap this function for
example to fully test _Terminate().
|
|
Remove _CPU_SMP_Processor_event_broadcast() and
_CPU_SMP_Processor_event_receive(). These functions are hard to use since they
are subject to the lost wake up problem.
|
|
The Cortex-R52 does not support cache coherency and the shareable memory
attribute. If a region is configured to be shareable, then it falls
back to use non-cacheable memory.
Update #4202.
|
|
Update #4202.
|
|
Update #4202.
|
|
The write to RBAR didn't have the valid flag set. Therefore the write to
RASR had an influence on the previously set region. That means for
example that if Region 0 had been enabled but 1 should be disabled due
to a size of 0, the previous code would have disabled region 0 instead.
This patch fixes that behaviour.
Close #4450
|
|
Don't initialze regions that have a negative size (for example due to a
wrong calculation).
Update #4450
|
|
Update #4202.
|
|
The __builtin_unreachable() cannot be used with current GCC versions to
tell the compiler that a function does not return to the caller, see:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99151
Add a no return variant of _CPU_Context_switch() to avoid generation of
dead code in _Thread_Start_multitasking() if RTEMS was built with SMP
support enabled.
|
|
Update #4202.
|
|
Update #4202.
|
|
Update #4202.
|
|
Somehow the table index has been missing in the latest patch version.
With that, the configuration for the first region has been applied
multiple times.
Update #4180
|
|
Update #4202.
|
|
Modify the MPU functions of the stm32h7 BSP to be table based and
available for all ARMV7M BSPs.
Update #4180
|
|
Provide RTEMS_NO_RETURN also in case RTEMS_DEBUG is defined to prevent errors
like this:
error: no return statement in function returning non-void [-Werror=return-type]
Use C11 and C++11 standard means to declare a no-return function.
Close #4122.
|
|
This introduces the CPU_USE_LIBC_INIT_FINI_ARRAY define for use by CPU
ports to determine which global constructor and destructor methods are
used instead of placing architecture defines where they shouldn't be.
Close #4018
|
|
Statically initialize the ARMv7-M vector table to allow a placement in
ROM with read-only MPU settings.
Change licence to BSD-2-Clause in some files.
|
|
Update #3835.
|
|
Update #3706.
|
|
Update #3706.
|
|
Update #3585.
|
|
Remove the CPU_PROVIDES_IDLE_THREAD_BODY option to avoid unnecessary
conditional compilation.
Close #3539.
|
|
Use the CPU_SIZEOF_POINTER alignment instead. The internal alignment
requirement is defined by the use of Chain_Node (consisting of two
pointers) to manage the free chain of partitions.
It seems that previously the condition
CPU_PARTITION_ALIGNMENT >= sizeof(Chain_Node)
was true on all CPU ports. Now, we need an additional check.
Update #3482.
|
|
On some architectures/simulators it is difficult to provoke an
exception with misaligned or illegal data loads. Use an illegal
instruction instead.
Update #3433.
|
|
This helps to reduce the use of architecture-specific defines throughout
the code base.
|
|
The context validation support functions _CPU_Context_validate() and
_CPU_Context_volatile_clobber() are used only by one test program
(spcontext01). Move the function declarations to the CPU port
implementation header file.
|
|
Statically initialize the interrupt stack area
(_Configuration_Interrupt_stack_area_begin,
_Configuration_Interrupt_stack_area_end, and
_Configuration_Interrupt_stack_size) via <rtems/confdefs.h>. Place the
interrupt stack area in a special section ".rtemsstack.interrupt". Let
BSPs define the optimal placement of this section in their linker
command files (e.g. in a fast on-chip memory).
This change makes makes the CPU_HAS_SOFTWARE_INTERRUPT_STACK and
CPU_HAS_HARDWARE_INTERRUPT_STACK CPU port defines superfluous, since the
low level initialization code has all information available via global
symbols.
This change makes the CPU_ALLOCATE_INTERRUPT_STACK CPU port define
superfluous, since the interrupt stacks are allocated by confdefs.h for
all architectures. There is no need for BSP-specific linker command
file magic (except the section placement), see previous ARM linker
command file as a bad example.
Remove _CPU_Install_interrupt_stack(). Initialize the hardware
interrupt stack in _CPU_Initialize() if necessary (e.g.
m68k_install_interrupt_stack()).
The optional _CPU_Interrupt_stack_setup() is still useful to customize
the registration of the interrupt stack area in the per-CPU information.
The initialization stack can reuse the interrupt stack, since
* interrupts are disabled during the sequential system initialization,
and
* the boot_card() function does not return.
This stack resuse saves memory.
Changes per architecture:
arm:
* Mostly replace the linker symbol based configuration of stacks with
the standard <rtems/confdefs.h> configuration via
CONFIGURE_INTERRUPT_STACK_SIZE. The size of the FIQ, ABT and UND
mode stack is still defined via linker symbols. These modes are
rarely used in applications and the default values provided by the
BSP should be sufficient in most cases.
* Remove the bsp_processor_count linker symbol hack used for the SMP
support. This is possible since the interrupt stack area is now
allocated by the linker and not allocated from the heap. This makes
some configure.ac stuff obsolete. Remove the now superfluous BSP
variants altcycv_devkit_smp and realview_pbx_a9_qemu_smp.
bfin:
* Remove unused magic linker command file allocation of initialization
stack. Maybe a previous linker command file copy and paste problem?
In the start.S the initialization stack is set to a hard coded value.
lm32, m32c, mips, nios2, riscv, sh, v850:
* Remove magic linker command file allocation of initialization stack.
Reuse interrupt stack for initialization stack.
m68k:
* Remove magic linker command file allocation of initialization stack.
Reuse interrupt stack for initialization stack.
powerpc:
* Remove magic linker command file allocation of initialization stack.
Reuse interrupt stack for initialization stack.
* Used dedicated memory region (REGION_RTEMSSTACK) for the interrupt
stack on BSPs using the shared linkcmds.base (replacement for
REGION_RWEXTRA).
sparc:
* Remove the hard coded initialization stack. Use the interrupt stack
for the initialization stack on the boot processor. This saves
16KiB of RAM.
Update #3459.
|
|
Add CPU port define for the interrupt stack alignment. The alignment
should take the stack ABI and the cache line size into account.
Update #3459.
|
|
Use the standard ARMv7-M systick module for the ARMv7-M CPU counter
instead of DWT counter since the DWT counter is affected by power saving
states.
Use an inline function for _CPU_Counter_difference() for all ARM BSPs.
Update #3456.
|
