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2023-05-20Update company nameSebastian Huber1-1/+1
The embedded brains GmbH & Co. KG is the legal successor of embedded brains GmbH.
2022-03-09SMP: Fix start multitasking for some targetsSebastian Huber1-0/+12
The previous SMP multitasking start assumed that the initial heir thread of a processor starts execution in _Thread_Handler(). The _Thread_Handler() sets the interrupt state explicitly by _ISR_Set_level() before it calls the thread entry. Under certain timing conditions, processors may perform an initial context switch to a thread which already executes its thread body (see smptests/smpstart01). In this case, interrupts are disabled after the context switch on targets which do not save/restore the interrupt state during a context switch (aarch64, arm, and riscv). Close #4627.
2022-02-28score/cpu/arm: Change license to BSD-2Joel Sherrill1-3/+22
Updates #3053.
2021-05-18score: Add _CPU_Context_switch_no_return()Sebastian Huber1-0/+3
The __builtin_unreachable() cannot be used with current GCC versions to tell the compiler that a function does not return to the caller, see: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99151 Add a no return variant of _CPU_Context_switch() to avoid generation of dead code in _Thread_Start_multitasking() if RTEMS was built with SMP support enabled.
2019-03-26score: Add ARM CPU architecture groupSebastian Huber1-1/+1
Update #3706.
2019-03-26score: Rename ScoreCPU Doxygen groupSebastian Huber1-1/+1
Update #3706.
2017-06-09Simplify TLS support in context switchSebastian Huber1-11/+2
There is no need to save the thread pointer in _CPU_Context_switch() since it is a thread invariant. It is initialized once in _CPU_Context_Initialize().
2017-03-28arm: Optimize context switchSebastian Huber1-18/+23
Set CPU_ENABLE_ROBUST_THREAD_DISPATCH to TRUE. In this case the interrupts are always enabled during a context switch even after interrupt processing (see #2751). Remove the CPSR from the context control since it contains only volatile bits. Close #2954.
2016-11-18arm: Use Per_CPU_Control::isr_dispatch_disableSebastian Huber1-2/+11
Update #2751.
2016-11-18score: Allow interrupts during thread dispatchSebastian Huber1-3/+7
Use a processor-specific interrupt frame during context switches in case the executing thread is longer executes on the processor and the heir thread is about to start execution. During this period we must not use a thread stack for interrupt processing. Update #2809.
2016-11-18arm: Use TPIDRPRW for current per-CPU controlSebastian Huber1-1/+1
Use the previously unused TPIDRPRW register to get the per-CPU control of the current processor. This avoids instructions in GET_SELF_CPU_CONTROL which are not available in Thumb mode.
2015-09-28SMP: Fix and optimize thread dispatchingSebastian Huber1-15/+12
According to the C11 and C++11 memory models only a read-modify-write operation guarantees that we read the last value written in modification order. Avoid the sequential consistent thread fence and instead use the inter-processor interrupt to set the thread dispatch necessary indicator.
2014-08-12arm: Add support for FPv4-SP floating point unitSebastian Huber1-2/+2
This floating point unit is available in Cortex-M4 processors and defined by ARMv7-M. This adds basic support for other VFP-D16 variants.
2014-07-04score: PR2183: Fix context switch on SMPSebastian Huber1-10/+46
Fix context switch on SMP for ARM, PowerPC and SPARC. Atomically test and set the is executing indicator of the heir context to ensure that at most one processor uses the heir context. Break the busy wait loop also due to heir updates.
2014-07-01arm: Use local label in _CPU_Context_restore()Sebastian Huber1-2/+2
2014-05-08score: Fix CPU context usage on SMPSebastian Huber1-11/+9
We must not alter the is executing indicator in _CPU_Context_Initialize() since this would cause an invalid state during a self restart. The is executing indicator must be valid at creation time since otherwise _Thread_Kill_zombies() uses an undefined value for not started threads. This could result in a system life lock.
2014-05-07score: Implement forced thread migrationSebastian Huber1-0/+20
The current implementation of task migration in RTEMS has some implications with respect to the interrupt latency. It is crucial to preserve the system invariant that a task can execute on at most one processor in the system at a time. This is accomplished with a boolean indicator in the task context. The processor architecture specific low-level task context switch code will mark that a task context is no longer executing and waits that the heir context stopped execution before it restores the heir context and resumes execution of the heir task. So there is one point in time in which a processor is without a task. This is essential to avoid cyclic dependencies in case multiple tasks migrate at once. Otherwise some supervising entity is necessary to prevent life-locks. Such a global supervisor would lead to scalability problems so this approach is not used. Currently the thread dispatch is performed with interrupts disabled. So in case the heir task is currently executing on another processor then this prolongs the time of disabled interrupts since one processor has to wait for another processor to make progress. It is difficult to avoid this issue with the interrupt latency since interrupts normally store the context of the interrupted task on its stack. In case a task is marked as not executing we must not use its task stack to store such an interrupt context. We cannot use the heir stack before it stopped execution on another processor. So if we enable interrupts during this transition we have to provide an alternative task independent stack for this time frame. This issue needs further investigation.
2014-03-21Change all references of rtems.com to rtems.org.Chris Johns1-1/+1
2014-02-04Add thread-local storage (TLS) supportSebastian Huber1-0/+10
Tested and implemented on ARM, m68k, PowerPC and SPARC. Other architectures need more work.
2013-12-03arm: Clear reservationsSebastian Huber1-1/+1
Recent GCC versions use atomic operations based on load/store exclusive in the C++ library.
2013-05-31smp: Add ARM supportSebastian Huber1-0/+3
2013-05-27arm: Fix CPSR and SPSR accessSebastian Huber1-2/+2
The GNU assembler translates for example a msr spsr, rN into msr SPSR_fc, rN This would update only a subset of the register and leads to an incomplete exceptions restore sequence resulting in system corruption. Correct is this: msr SPSR_fsxc, rN
2013-05-10arm: Support VFP-D32 and NeonSebastian Huber1-1/+11
2012-05-11Remove All CVS Id Strings Possible Using a ScriptJoel Sherrill1-2/+0
Script does what is expected and tries to do it as smartly as possible. + remove occurrences of two blank comment lines next to each other after Id string line removed. + remove entire comment blocks which only exited to contain CVS Ids + If the processing left a blank line at the top of a file, it was removed.
2011-09-242011-09-24 Sebastian Huber <sebastian.huber@embedded-brains.de>Sebastian Huber1-0/+4
* rtems/score/armv7m.h, armv7m-context-initialize.c, armv7m-context-restore.c, armv7m-context-switch.c, armv7m-exception-handler-get.c, armv7m-exception-handler-set.c, armv7m-exception-priority-get.c, armv7m-exception-priority-set.c, armv7m-initialize.c, armv7m-isr-dispatch.c, armv7m-isr-enter-leave.c, armv7m-isr-level-get.c, armv7m-isr-level-set.c, armv7m-isr-vector-install.c, armv7m-multitasking-start-stop.c: New files. * Makefile.am, preinstall.am: Reflect changes above. * rtems/score/arm.h: Define ARM_MULTILIB_ARCH_V4 and ARM_MULTILIB_ARCH_V7M. * rtems/score/cpu.h, cpu_asm.S, cpu.c, arm_exc_abort.S, arm_exc_handler_high.c, arm_exc_handler_low.S, arm_exc_interrupt.S: Define CPU_HAS_HARDWARE_INTERRUPT_STACK to FALSE. Use ARM_MULTILIB_ARCH_V4 and ARM_MULTILIB_ARCH_V7M.
2010-04-08add/adapt documentationThomas Doerfler1-0/+8
2010-03-272010-03-27 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill1-0/+4
* arm_exc_abort.S, arm_exc_handler_high.c, arm_exc_handler_low.S, arm_exc_interrupt.S, cpu.c, cpu_asm.S: Add include of config.h
2009-12-04Whitespace removal.Ralf Corsepius1-3/+3
2009-09-18 * rtems/score/cpu.h: Fix for inline asm in _CPU_Fatal_halt().Thomas Doerfler1-20/+2
* rtems/asm.h: Added macro to define ARM functions. * cpu_asm.S, arm_exc_handler_low.S: Use macro from above.
2009-07-17exception handler maintenanceThomas Doerfler1-130/+0
2007-11-262007-11-26 Ray Xu <rayx.cn@gmail.com>Joel Sherrill1-0/+3
* cpu.c, score/cpu.h: Fix headers. Remove extra inline definition. * cpu_asm.S: Note origin of Thumb support.
2007-11-062007-11-03 Ray Xu <rayx.cn@gmail.com>Joel Sherrill1-13/+62
* cpu.c, cpu_asm.S, score/cpu.h : add support for ARM<->THUMB veneer thumb new dir to controll CPSR/SPRS in thumb mode 2007-05-09 Ray Xu <rayx.cn@gmail.com> * cpu.c: move do_data_abort() to libbsp/arm/shared/abort/ implement a compact do_data_abort() in simple_abort.c
2006-06-022006-06-02 Jay Monkman <jtm@lopingdog.com>Jay Monkman1-5/+15
* cpu.c, cpu_asm.S: Fixed ARM Data Abort handling.
2004-04-012004-04-01 Ralf Corsepius <ralf_corsepius@rtems.org>Ralf Corsepius1-1/+1
* cpu_asm.S: Include <rtems/asm.h> instead of <asm.h>.
2003-09-042003-09-04 Joel Sherrill <joel@OARcorp.com>Joel Sherrill1-1/+1
* asm.h, cpu.c, cpu_asm.S, rtems/score/arm.h, rtems/score/cpu.h, rtems/score/cpu_asm.h, rtems/score/types.h: URL for license changed.
2002-07-302002-07-30 Jay Monkman <jtm@smoothsmoothie.com>Joel Sherrill1-87/+25
* cpu.c, cpu_asm.S, rtems/score/arm.h, rtems/score/cpu.h, rtems/score/cpu_asm.h, rtems/score/types.h: ARM port works well enough to run all sptests, tmtests, and ttcp. In addition to general cleanup, there has been considerable optimization to interrupt disable/enable, endian swapping, and context switching.
2002-07-172002-07-17 Jay Monkman <jtm@smoothsmoothie.com>Joel Sherrill1-48/+71
* rtems/score/cpu_asm.h: Enhanced to include register offsets. * Makefile.am: Install rtems/score/cpu_asm.h. * cpu.c: Significantly enhanced including the implementation of _CPU_ISR_Get_level. * cpu_asm.S: Improved behavior of context switch and interrupt dispatching. * rtems/score/arm.h: Improved the CPU model name determination. * rtems/score/cpu.h: Improved interrupt disable/enable functions.
2000-07-27Port of RTEMS to the ARM processor family by Eric ValetteJoel Sherrill1-0/+193
<valette@crf.canon.fr> and Emmanuel Raguet <raguet@crf.canon.fr> of Canon CRF - Communication Dept. This port includes a basic BSP that is sufficient to link hello world.
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