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* Do not use RTEMS_INLINE_ROUTINESebastian Huber2022-09-192-4/+4
| | | | | | | Directly use "static inline" which is available in C99 and later. This brings the RTEMS implementation closer to standard C. Close #3935.
* score: Remove _CPU_Counter_difference()Sebastian Huber2022-09-091-8/+0
| | | | | | | All CPU ports used the same _CPU_Counter_difference() implementation. Remove this CPU port interface and mandate a monotonically increasing CPU counter. Close #3456.
* cpu.h: Fix gcc 12 warningsRyan Long2022-08-191-2/+18
| | | | | | | | Added two pragmas to address, and changed the value of AARCH64_EXCEPTION_MAKE_ENUM_64_BIT to INT_MAX because the old value was not in range of an int. Updates #4662
* cpukit/libdl: Add support for AArch64Ryan Long2022-07-291-0/+256
| | | | | | rtl-mdreloc-aarch64.c and elf_machdep.h came from NetBSD. Updates #4682
* aarch64: Use page table level 0Kinsey Moore2022-07-211-1/+0
| | | | | | | | | This alters the AArch64 page table generation and mapping code and MMU configuration to use page table level 0 in addition to levels 1, 2, and 3. This allows the mapping of up to 48 bits of memory space and is the maximum that can be mapped without relying on additional processor extensions. Mappings are restricted based on the number of physical address bits that the CPU supports.
* cpukit/aarch64: Remove _CPU_ISR_install_vectorKinsey Moore2022-07-052-31/+0
| | | | This function was never actually used and is dead code.
* score: Add _CPU_Use_thread_local_storage()Sebastian Huber2022-07-041-0/+9
| | | | | | | | | | | | At some point during system initialization, the idle threads are created. Afterwards, the boot processor basically executes within the context of an idle thread with thread dispatching disabled. On some architectures, the thread-local storage area of the associated thread must be set in dedicated processor registers. Add the new CPU port function to do this: void _CPU_Use_thread_local_storage( const Context_Control *context ) Close #4672.
* score/cpu: Silence ARM and AARCH64 GCC 12 false trigger array warningChris Johns2022-06-151-0/+3
| | | | | | | | | | | | The false trigger is covered in: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99578 GCC 11 and 12 has been patched for constant pointer casts above 4K. This code casts a constant pointer within the first 4K page. As a result the patch disables the warning. Updates #4662
* cpukit/aarch64: Add Per_CPU_Control accessorKinsey Moore2022-03-121-0/+23
| | | | | | Add an architecture-specific implementation for _CPU_Get_current_per_CPU_control() to reduce overhead for getting the current CPU's Per_CPU_Control structure.
* SMP: Fix start multitasking for some targetsSebastian Huber2022-03-092-0/+21
| | | | | | | | | | | | | The previous SMP multitasking start assumed that the initial heir thread of a processor starts execution in _Thread_Handler(). The _Thread_Handler() sets the interrupt state explicitly by _ISR_Set_level() before it calls the thread entry. Under certain timing conditions, processors may perform an initial context switch to a thread which already executes its thread body (see smptests/smpstart01). In this case, interrupts are disabled after the context switch on targets which do not save/restore the interrupt state during a context switch (aarch64, arm, and riscv). Close #4627.
* bsps/aarch64: Set interrupt level correctlyKinsey Moore2021-11-011-5/+11
| | | | | | The existing code is functional but inccorrect and blindly modifies the other masking bits. It is important to preserve those other bits since they control masking of important system events.
* aarch64: Break out MMU definitionsKinsey Moore2021-11-011-0/+97
| | | | | | This moves the AArch64 MMU memory type definitions into cpukit for use by libdebugger since remapping of memory is required to insert software breakpoints.
* cpukit/aarch64: Use correct debug register namesKinsey Moore2021-11-011-16/+1096
| | | | | | | The N used in the breakpoint and watchpoint register names is intended to be an integer between 0 and 15 (inclusive) and will not compile when used as is. This adds the accessors necessary to access all of these breakpoint and watchpoint registers.
* cpukit/aarch64: Add exception extensions supportKinsey Moore2021-10-294-84/+292
| | | | | This adds the function implementations necessary to add exception extensions support to AArch64.
* cpukit/aarch64: Use correct interrupt level typesKinsey Moore2021-10-012-4/+4
| | | | | All other architectures use uint32_t for interrupt levels and there is no reason not to do so on AArch64.
* cpukit/aarch64: Use correct context register setsKinsey Moore2021-10-012-55/+123
| | | | | | | Context validation for AArch64 was ported from the ARM implementation without a reinterpretation of the actual requirements. The spcontext01 test just happened to pass because the set of scratch registers in ARM is a subset of the scratch registers in AArch64.
* cpukit: Add AArch64 SMP SupportKinsey Moore2021-09-215-9/+160
| | | | This adds SMP support for AArch64 in cpukit and for the ZynqMP BSPs.
* Turn off executable permissions for a number of source filesJoel Sherrill2021-08-091-0/+0
| | | | | | | Cloning under Cygwin turned off executable permission on these files. This shows them as modified even though they have not explicitly been touched. Executable permission should not have been on for these files so this is just a minor clean up.
* score: Canonicalize _CPU_Fatal_halt()Sebastian Huber2021-07-283-15/+16
| | | | | | | | Move _CPU_Fatal_halt() declaration to <rtems/score/cpuimpl.h> and make sure it is a proper declaration of a function which does not return. Fix the type of the error code. If necessary, add the implementation to cpu.c. Implementing _CPU_Fatal_halt() as a function makes it possible to wrap this function for example to fully test _Terminate().
* score: Remove processor event broadcast/receiveSebastian Huber2021-07-281-12/+0
| | | | | | Remove _CPU_SMP_Processor_event_broadcast() and _CPU_SMP_Processor_event_receive(). These functions are hard to use since they are subject to the lost wake up problem.
* bsps/aarch64: Add MMU driver to relax alignmentKinsey Moore2021-05-271-16/+50
| | | | | | | | | | | | | | | Currently, the AArch64 BSPs have a hard time running on real hardware without building the toolchain and the bsps with -mstrict-align in multiple places. Configuring the MMU on these chips allows for unaligned memory accesses for non-device memory which avoids requiring strict alignment in the toolchain and in the BSPs themselves. In writing this driver, it was found that the synchronous exception handling code needed to be rewritten since it relied on clearing SCTLR_EL1 to avoid thread stack misalignments in RTEMS_DEBUG mode. This is now avoided by exactly preserving thread mode stack and flags and the new implementation is compatible with the draft information provided on the mailing list covering the Exception Management API.
* bsps/aarch64: Break out system registersKinsey Moore2021-05-271-0/+9985
| | | | | Break out system register definitions and accessors so that they're usable by other parts of RTEMS.
* score/aarch64: Align context validation frameKinsey Moore2021-05-261-11/+18
| | | | | | Ensure the stack remains aligned by keeping the context frame at a multiple of 16 bytes. This avoids stack alignment exceptions which occur when the stack pointer is not 16 byte aligned.
* cpukit/aarch64: Restore ISR cookie bit maskKinsey Moore2021-04-191-13/+13
| | | | | | | The _CPU_ISR_Is_enabled() function operates on ISR cookies and so must mask off the appropriate status bits. This also fixes the naming of the parameters of the _CPU_ISR_* functions to indicate use of ISR cookies instead of interrupt enable/disable levels.
* cpukit/aarch64: Add ESR register decodingAlex White2021-04-061-10/+125
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* bsps/aarch64: RTEMS_DEBUG stack alignment faultsKinsey Moore2021-03-051-2/+8
| | | | | | Run with stack alignment faults enabled under RTEMS_DEBUG to catch any stack misalignments early. This makes it easier to track them down should they ever occur.
* score/aarch64: Fix interrupt level readsAlex White2021-03-052-3/+7
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* aarch64: Fix context switchSebastian Huber2021-03-051-2/+2
| | | | | | The Per_CPU_Control::isr_dispatch_disable is a 32-bit integer. Close #4206.
* cpukit/aarch64: Add explanation of exception flowKinsey Moore2020-12-102-3/+18
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* cpukit/aarch64: Use hex consistently for offsetsKinsey Moore2020-12-105-116/+116
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* score/aarch64: Resolve warning in exception dumpKinsey Moore2020-11-241-2/+2
| | | | | This resolves a warning in the exception frame dump for AArch64 relating to a missized printf format specifier.
* score/aarch64: Size saved SP register for ABIKinsey Moore2020-11-131-1/+4
| | | | | This ensures that the saved SP register is sized appropriately depending on the chosen ABI and prevents a warning in the libmisc stack checker.
* rtems: Improve RTEMS_NO_RETURN attributeSebastian Huber2020-10-101-2/+1
| | | | | | | | | | | Provide RTEMS_NO_RETURN also in case RTEMS_DEBUG is defined to prevent errors like this: error: no return statement in function returning non-void [-Werror=return-type] Use C11 and C++11 standard means to declare a no-return function. Close #4122.
* score: Add AArch64 portKinsey Moore2020-10-0516-0/+2751
This adds a CPU port for AArch64(ARMv8) with support for exceptions and interrupts.