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Casts from uint64_t to void* must go through a uintptr_t cast to avoid
warnings when building with the ILP32 ABI since this is otherwise an
implicit truncation to 32bits for a pointer.
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Add _CPU_Get_TLS_thread_pointer() to get the thread pointer which is
used to get the address of thread-local storage objects associated with
a thread.
Update #4920.
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The MAIR index currently assigned (1) for uncached memory segments is
not configured properly for this purpose. Instead, this switches
uncached memory segment flags to MAIR index 2 which is properly
configured for uncached inner and outer shareable domains.
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These functions do not belong to an super core service.
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All CPU ports used the same <rtems/score/cpustdatomic.h> header file to
provide the atomic operations. Remove the header file indirection.
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The embedded brains GmbH & Co. KG is the legal successor of embedded
brains GmbH.
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The AArch64 TRM specifies that when FPCR is set to trap floating point
exceptions, the FPSR exception bits are not set. This ensures that FPSR
is updated as FENV expects even if floating point exception traps are
enabled.
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Update #3835.
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For most CPU ports this was already the case. This makes it possible to use
the size as an object alignment using RTEMS_ALIGNED().
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Directly use "static inline" which is available in C99 and later. This brings
the RTEMS implementation closer to standard C.
Close #3935.
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All CPU ports used the same _CPU_Counter_difference() implementation. Remove
this CPU port interface and mandate a monotonically increasing CPU counter.
Close #3456.
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Added two pragmas to address, and changed the value of
AARCH64_EXCEPTION_MAKE_ENUM_64_BIT to INT_MAX because the old value was not
in range of an int.
Updates #4662
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rtl-mdreloc-aarch64.c and elf_machdep.h came from NetBSD.
Updates #4682
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This alters the AArch64 page table generation and mapping code and MMU
configuration to use page table level 0 in addition to levels 1, 2, and
3. This allows the mapping of up to 48 bits of memory space and is the
maximum that can be mapped without relying on additional processor
extensions. Mappings are restricted based on the number of physical
address bits that the CPU supports.
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This function was never actually used and is dead code.
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At some point during system initialization, the idle threads are created.
Afterwards, the boot processor basically executes within the context of an idle
thread with thread dispatching disabled. On some architectures, the
thread-local storage area of the associated thread must be set in dedicated
processor registers. Add the new CPU port function to do this:
void _CPU_Use_thread_local_storage( const Context_Control *context )
Close #4672.
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The false trigger is covered in:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99578
GCC 11 and 12 has been patched for constant pointer casts above
4K. This code casts a constant pointer within the first 4K
page. As a result the patch disables the warning.
Updates #4662
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Add an architecture-specific implementation for
_CPU_Get_current_per_CPU_control() to reduce overhead for getting the
current CPU's Per_CPU_Control structure.
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The previous SMP multitasking start assumed that the initial heir thread of a
processor starts execution in _Thread_Handler(). The _Thread_Handler() sets
the interrupt state explicitly by _ISR_Set_level() before it calls the thread
entry. Under certain timing conditions, processors may perform an initial
context switch to a thread which already executes its thread body (see
smptests/smpstart01). In this case, interrupts are disabled after the context
switch on targets which do not save/restore the interrupt state during a
context switch (aarch64, arm, and riscv).
Close #4627.
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The existing code is functional but inccorrect and blindly modifies the
other masking bits. It is important to preserve those other bits since
they control masking of important system events.
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This moves the AArch64 MMU memory type definitions into cpukit for use
by libdebugger since remapping of memory is required to insert software
breakpoints.
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The N used in the breakpoint and watchpoint register names is intended
to be an integer between 0 and 15 (inclusive) and will not compile when
used as is. This adds the accessors necessary to access all of these
breakpoint and watchpoint registers.
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This adds the function implementations necessary to add exception
extensions support to AArch64.
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All other architectures use uint32_t for interrupt levels and there is
no reason not to do so on AArch64.
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Context validation for AArch64 was ported from the ARM implementation
without a reinterpretation of the actual requirements. The spcontext01
test just happened to pass because the set of scratch registers in ARM
is a subset of the scratch registers in AArch64.
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This adds SMP support for AArch64 in cpukit and for the ZynqMP BSPs.
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Cloning under Cygwin turned off executable permission on these
files. This shows them as modified even though they have not
explicitly been touched. Executable permission should not have
been on for these files so this is just a minor clean up.
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Move _CPU_Fatal_halt() declaration to <rtems/score/cpuimpl.h> and make sure it
is a proper declaration of a function which does not return. Fix the type of
the error code. If necessary, add the implementation to cpu.c. Implementing
_CPU_Fatal_halt() as a function makes it possible to wrap this function for
example to fully test _Terminate().
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Remove _CPU_SMP_Processor_event_broadcast() and
_CPU_SMP_Processor_event_receive(). These functions are hard to use since they
are subject to the lost wake up problem.
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Currently, the AArch64 BSPs have a hard time running on real hardware
without building the toolchain and the bsps with -mstrict-align in
multiple places. Configuring the MMU on these chips allows for unaligned
memory accesses for non-device memory which avoids requiring strict
alignment in the toolchain and in the BSPs themselves.
In writing this driver, it was found that the synchronous exception
handling code needed to be rewritten since it relied on clearing SCTLR_EL1 to
avoid thread stack misalignments in RTEMS_DEBUG mode. This is now
avoided by exactly preserving thread mode stack and flags and the new
implementation is compatible with the draft information provided on the
mailing list covering the Exception Management API.
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Break out system register definitions and accessors so that they're
usable by other parts of RTEMS.
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Ensure the stack remains aligned by keeping the context frame at a
multiple of 16 bytes. This avoids stack alignment exceptions which occur
when the stack pointer is not 16 byte aligned.
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The _CPU_ISR_Is_enabled() function operates on ISR cookies and so must
mask off the appropriate status bits. This also fixes the naming of the
parameters of the _CPU_ISR_* functions to indicate use of ISR cookies
instead of interrupt enable/disable levels.
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Run with stack alignment faults enabled under RTEMS_DEBUG to catch any
stack misalignments early. This makes it easier to track them down
should they ever occur.
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The Per_CPU_Control::isr_dispatch_disable is a 32-bit integer.
Close #4206.
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This resolves a warning in the exception frame dump for AArch64 relating
to a missized printf format specifier.
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This ensures that the saved SP register is sized appropriately depending
on the chosen ABI and prevents a warning in the libmisc stack checker.
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Provide RTEMS_NO_RETURN also in case RTEMS_DEBUG is defined to prevent errors
like this:
error: no return statement in function returning non-void [-Werror=return-type]
Use C11 and C++11 standard means to declare a no-return function.
Close #4122.
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This adds a CPU port for AArch64(ARMv8) with support for exceptions and
interrupts.
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