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The ARM C++ exception ABI uses an address ordered index table to
locate the correct frame data and this requires the EXIDX sections are
loaded in the order the order the matching text is loaded.
The EXIDX sections set the SHF_LINK_ORDER flag and link field. This patch
adds support to load those flagged sections in the linked-to section
order.
Updates #2955.
Closes #2959
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This has been tested on SPARC, i386, PowerPC and ARM.
Closes #2767.
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Use of rtems_cache_get_maximal_line_size() is more descriptive
choice. The min/max data/instruction cache line size is not critical
there, value is used for optimization only to use single operation
for directly following sections.
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Memory content changes caused by relocation has to be
propagated to memory/cache level which is used/snooped
during instruction cache fill.
Closes #2438
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Synchronize each cluster of sections of the same type separately
to support even cases where text and data are allocated from different
areas (for example due allocation from different MPU protection regions).
rtems_cache_instruction_sync_after_code_change is called even to data
sections. Propagation of data only changes should not require cache
maintenance operation on sane SMP mutithread capable systems if barrier
instruction is added but be on safe side even for case where self
modifying code uses data sections initial values etc.
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This is a merge of the RTL project.
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