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* bsp/altera-cyclone-v: Move MMU configuration tableSebastian Huber2014-07-013-20/+37
| | | | This makes it possible to use application specific version.
* bsps/arm: Rename bsp_mm_config_tableSebastian Huber2014-07-013-11/+9
| | | | | | Rename bsp_mm_config_table to arm_cp15_start_mmu_config_table and rename bsp_mm_config_table_size to arm_cp15_start_mmu_config_table_size to be in line with the other names in <bsp/arm-cp15-start.h>.
* bsps/sparc: Reduce copy and pasteSebastian Huber2014-07-015-58/+28
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* LEON3: devfs free nodes must be sizedDaniel Hellstrom2014-06-301-0/+3
| | | | | | | | | .. according to the maximum number of termios ports which is 8. Since LEON3 uses PnP to find how many UARTs there are present we must make sure worst case work. The current maximum of 4 free nodes caused for example the GR712RC with its 6 UARTs to fail during devfs02 test.
* LEON3: fix console close handlingDaniel Hellstrom2014-06-301-3/+3
| | | | | | On SMP rtems_interrupt_lock_context must be used. Most tests fail with a NULL pointer exception when exiting, except on NGMP where main memory is at 0x00000000.
* bsp/realview-pbx-a9: Fix SMP startupSebastian Huber2014-06-121-0/+14
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* lm3s6965-testsuite.cfg: Add pppd.Martin Galvan2014-06-101-0/+1
| | | | | | When trying to compile RTEMS for the Stellaris LM3S6965 board, I had an issue of pppd.exe's .rodata section being too big to fit in the board's memory image (region 'ROM_INT' overflowed).
* bsp/lpc176x: New BSPMartin Boretto2014-06-1042-0/+6504
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* Revert "bsps/powerpc: Fix potential relocation truncation"Sebastian Huber2014-06-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit d9ff8b3e687a0ec56cac6463ba01ba7775eccd41. It is not that simple: https://sourceware.org/ml/binutils/2014-06/msg00062.html On Fri, Jun 06, 2014 at 01:31:48PM +0200, Sebastian Huber wrote: > On 2014-06-06 13:23, Sebastian Huber wrote: > >Ok, so this "cmplwi cr0, rX, ppc_exc_lock_std@sdarel" is illegal, > >since > >ppc_exc_lock_std@sdarel is signed and the immediate is unsigned > >16-bit? The > >assembler doesn't issue a warning about this. > > > >Exists there a way to rescue this cmplwi hack without relaxing the > >overflow > >checks? > > Hm, sorry, it was surprisingly simple. This works: > > "cmplwi cr0, rX, ppc_exc_lock_std@sdarel@l" > > I was not aware that you can add several @ in a row. That is the wrong thing to use here. sdarel@l translates to a VLE reloc which applies to a split 16-bit field in VLE insns. You want cmpwi cr0, rX, ppc_exc_lock_std@sdarel to properly compare a 16-bit signed number from sym@sdarel. Note that the assembler does error if you write something like cmplwi 3,-30000 or cmpwi 3,40000 so what the linker is now doing is extending this behaviour to link time.
* bsps/powerpc: Fix potential relocation truncationSebastian Huber2014-06-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | See also https://sourceware.org/ml/binutils/2014-06/msg00059.html On Fri, Jun 06, 2014 at 11:01:10AM +0200, Sebastian Huber wrote: > I performed a git bisect and found this: > > 93d1b056cb396d6468781fe0e40dd769891bed32 is the first bad commit > commit 93d1b056cb396d6468781fe0e40dd769891bed32 > Author: Alan Modra <amodra@gmail.com> > Date: Tue May 20 11:42:42 2014 +0930 > > Rewrite ppc32 backend .sdata and .sdata2 handling Hmm, I'm surprised that your git bisect found this patch. Was _SDA_BASE_ set differently before this? > 0x00000000000dfc00 _SDA_BASE_ > 0x00000000000d7f78 ppc_exc_lock_std > 4b8: 28 05 00 00 cmplwi r5,0 > 4ba: R_PPC_SDAREL16 ppc_exc_lock_std ppc_exc_lock_std@sdarel will be calculating 0xd7f78 - 0xdfc00 which is 0xf...fff8378, and that falls foul of commit 86c9573369616e7437481b6e5533aef3a435cdcf Author: Alan Modra <amodra@gmail.com> Date: Sat Mar 8 13:05:06 2014 +1030 Better overflow checking for powerpc32 relocations cmplwi has an *unsigned* 16-bit field, and we now check the overflow properly. I wonder how many more of these we'll hit, and whether the uproar will be enough that I'll be forced to relax the checks?
* bsps/arm: Fix TLB invalidation for ARMv7-ASebastian Huber2014-06-061-0/+7
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* bsps/arm: Fix Cortex-A9 MPCore clock driverSebastian Huber2014-06-061-9/+18
| | | | | | The nanoseconds extension returned wrong values on secondary processors since some of the global timer registeres are banked. Use global variables instead.
* bsp/altera-cyclone-v: Enable unified L2 cacheSebastian Huber2014-06-062-1/+12
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* bsp/altera-cyclone-v: Move SMP supportSebastian Huber2014-06-063-54/+94
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* bsps/arm: Change L2 cache initializationSebastian Huber2014-06-062-50/+1
| | | | | Do not touch the L1 caches since they have been initialized by the start hooks.
* bsp/altera-cyclone-v: Simplify start hooksSebastian Huber2014-06-061-120/+25
| | | | Use arm_a9mpcore_start_hook_0(). The L2 cache is now disabled.
* bsp/altera-cyclone-v: Change default baudSebastian Huber2014-06-061-1/+1
| | | | Use value for standard U-Boot.
* bsp/altera-cyclone-v: Use NOLOAD for nocache secSebastian Huber2014-06-061-1/+1
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* bsp/altera-cyclone-v: Simplify MMU config tableSebastian Huber2014-06-061-2/+1
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* bsps/arm: Define ARM_CP15_TEXT_SECTIONSebastian Huber2014-06-069-44/+18
| | | | | Define ARM_CP15_TEXT_SECTION to BSP_START_TEXT_SECTION so that the start code is in the right section.
* bsps/arm: Add ARM_CP15_TEXT_SECTIONSebastian Huber2014-06-051-63/+134
| | | | | Allow users of this header file to optionally place the inline functions into a non-standard section.
* bsps/arm: Simplify L1 caches supportSebastian Huber2014-06-051-55/+12
| | | | Delete superfluous/incorrect interrupt disable/enable.
* bsps/arm: Add all level data cache invalidationSebastian Huber2014-06-051-2/+63
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* bsps/arm: TypoSebastian Huber2014-06-051-1/+1
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* bsps/arm: Cortex-A9 MPCore startSebastian Huber2014-06-051-0/+5
| | | | Invalidate entire branch predictor array.
* bsps/arm: Cortex-A9 MPCore startSebastian Huber2014-06-051-4/+4
| | | | Enable SCU only on the boot processor.
* bsps/arm: Cortex-A9 MPCore startSebastian Huber2014-06-051-6/+13
| | | | Add arm_a9mpcore_start_enable_smp_in_auxiliary_control().
* bsps/arm: Simplify Cortex-A9 MPCore startSebastian Huber2014-06-051-31/+32
| | | | | Add arm_a9mpcore_start_on_secondary_processor(). Rely on error checks in _SMP_Start_multitasking_on_secondary_processor().
* LEON2: enable exception prinout by defaultDaniel Hellstrom2014-06-051-1/+1
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* LEON3: enable exception prinout by defaultDaniel Hellstrom2014-06-051-1/+1
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* GRETH: remove TCP/UDP HW checksum generationDaniel Hellstrom2014-06-051-2/+2
| | | | The GRETH doesn't support IP fragments.
* score/sparc: Add support for paravirtualizationChristian Mauderer2014-06-036-1/+76
| | | | | | | Guest systems in paravirtualization environments run usually in user mode. Thus it is not possible to directly access the PSR and TBR registers. Use functions instead of inline assembler to access these registers if RTEMS_PARAVIRT is defined.
* mrm332: Tests now build and fewer warningsJoel Sherrill2014-06-014-12/+10
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* m68k/shared/misc/memProbe.c: Add prototype to eliminate warningJoel Sherrill2014-06-011-0/+2
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* bsps/gdbarmsim: Add the missing bspstarthooks.c.Chris Johns2014-05-301-0/+20
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* SPARC: syscall optimizations and PSR-write fixDaniel Hellstrom2014-05-282-15/+24
| | | | | | | | | | | | | | | The last optimization missed was incorrect in regards to PSR write instruction delay must be 3 instructions. New optimizations: * align to 32-byte cache line. * rearrange code into three "blocks" of 4 instructions that is executed by syscall 2 and 3. This is to optimize for 16/32 byte cache lines. * use delay-slot instruction in trap table to reduce by one instruction. * use the fact that "wr %PSR" implements XOR to reduce by one instruction.
* LEON3: coding style clean bsp_irq_fixup()Daniel Hellstrom2014-05-281-9/+9
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* LEON3: add support for IRQ16..31 for CPU!=0Daniel Hellstrom2014-05-281-2/+3
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* bsps: Do not build tests that require a tick interrupt.Chris Johns2014-05-2821-0/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following BSPs do not have tick support so the tests fail: arm1136jfs arm1136js arm7tdmi arm920 armcortexa9 (does not run any more) avrtest h8sim h8sxsim m32csim m32rsim moxiesim simsh1 simsh2 simsh4 v850e1sim v850e2sim v850e2v3sim v850esim v850essim v850sim This list was provided by Joel in the following post: http://www.rtems.org/pipermail/rtems-devel/2014-April/006526.html
* bsp/altera-cyclone-v: CleanupRalf Kirchner2014-05-281-3/+3
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* bsp/altera-cyclone-v: Reduce size of nocache heapRalf Kirchner2014-05-282-4/+4
| | | | Network mbufs and clusters now are cached. Thus the nocache heap can get reduced to 1 MByte.
* bsp/altera-cyclone-v: Cache mbufs and clustersRalf Kirchner2014-05-281-12/+0
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* bsp/altera-cyclone-v: Enable L2 cache for network driverRalf Kirchner2014-05-281-1/+14
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* bsp/altera-vyclone-v: Broadcast cache maintenancesRalf Kirchner2014-05-281-3/+3
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* bsp/arm: Broadcast cache maintenancesRalf Kirchner2014-05-281-1/+1
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* bsps/sparc: Change tabs to spaces.Daniel Cederman2014-05-2718-311/+309
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* bsps/sparc: Add copyright and license informationDaniel Cederman2014-05-2720-38/+157
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* bsps/sparc: Make lines in SPARC BSPs adhere to 80 character limit.Daniel Cederman2014-05-2721-183/+292
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* bsp/gdbarmsim: Switch to the standard arm/shared/startup.Chris Johns2014-05-265-402/+143
| | | | | | | Switch to the standard ARM startup code. This requires adding the standard interrupt code. The interrupt code does nothing at this point in time. I do not know if the ARM simulator in GDB supports interrupts.
* bsp/gdbarmsim: Change syscall functions to not clash with RTEMS functions.Chris Johns2014-05-263-175/+104
| | | | | | | | | | | | The syscall functions overlapped with RTEMS, for example _write, _read, etc. Change these to be internal to the BSP and avoid any clash with names in RTEMS. Add support for SWI_Write0. Change the console driver to use SWI_Write0. This outputs the character to the host's stdout. Writing to file name 0 is not captured and managed by GDB's simulation code while the SWI_Write0 is. The managed stdout data is encapulated in the MI protocol while writes to file handle 0 are dropped by GDB when in MI mode.
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