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* arm/xilinx_zynq: Start the second core when an SMP build.Chris Johns2016-09-012-0/+22
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* arm/xilinx_zynq: ensure that cache is cleaned and MMU disabled when ↵Pavel Pisa2016-09-011-0/+35
| | | | | | | | | initialization starts. The u-boot loader enables the MMU plus the data and instruction caches in some versions which results in RTEMS boot failure. Closes #2774.
* libdl: The dl04 is too big for some BSPs. Do not built it.Chris Johns2016-08-303-0/+3
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* arm/raspberrypi: Mailbox : Extending functionalityMudit Jain2016-08-273-0/+130
| | | | | Adding functionality to get board serial, power state & clock rate
* bsp/atsam: Add missing break statementAlexander Krutwig2016-08-241-0/+1
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* bsp/atsam: Fix data cache flushAlexander Krutwig2016-08-241-3/+7
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* libbsp/arm: Fix ARM BSPs missing the bsp_translation_table_end symbol.Chris Johns2016-08-232-0/+2
| | | | Closes #2775.
* bsp/atsam: Add timeout to QSPI send commandAlexander Krutwig2016-08-181-1/+16
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* libbsp/arm: Add the TTB table to the default MMU set up as read/write.Chris Johns2016-08-151-0/+4
| | | | | | | This lets the table be changed at runtime for dynamic loading and debugger support. Closes #2775.
* librtems++: Remove from RTEMS.Chris Johns2016-08-1120-2462/+0
| | | | | | | This is old and there are better design patterns for threading and C++. We recommend you use the new C++ standards based support. Closes #2777.
* build-system: Always enable C++ if the compiler is present.Chris Johns2016-08-113-18/+26
| | | | | | | | | | | We always build a C++ compiler and building with C++ does not effect RTEMS or the runtime. This patch always enabled the support. There is no need to manually enable it any more. You can disable C++ with '--disable-cxx'. If an architecture does not have a C++ compiler support is automatically disabled.
* bsp/atsam: Add power supportAlexander Krutwig2016-08-087-0/+505
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* atsam: Add atsam_rtc_get_time()Alexander Krutwig2016-08-082-16/+23
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* arm/raspberrypi: framebuffer driver checks for initialization and tries ↵Pavel Pisa2016-07-311-1/+11
| | | | | | | | | | | | | | | runtime init if required. Code works but there is problem how to setup caching for the regions (arm_cp15_set_translation_table_entries arguments). If ARMV7_MMU_DATA_READ_WRITE_CACHED is used then CPU accesses are noncoherent with VideoCore and some part of image update are not visible until pushed from cache by other activities. If ARMV7_MMU_DATA_READ_WRITE is used then access is extremely slow. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* arm/raspberrypi: VideoCore access corrections in cache operation and more ↵Pavel Pisa2016-07-316-48/+112
| | | | | | | | | | | | | | | | | | | | | | | | | | | | error checking. The first, mistake in buffer size computation for cache flush and invalidate has been corrected. GCC __attribute__( ( aligned( 64 ) ) ) should work and works for local variables. Code ensures right stack alignment. But attribute has to be moved to type declaration to ensure that structure size is affected by attribute. But even this seems to not work reliably for some reason. May it be, the stack area between frame start and end of local variable buffer accessed during context switch or some stack prefetch during resturn such way that some cache lines belonging to buffer are filled to cache. Extending buffer by one more cache line padding helps there. In the longer term perspective, buffer should be moved to some static area or cache aligned dynamic memory allocated. Concurrent calls to the VideoCore operations and access serialization should be added too but problem is that some calls are required during workspace and MMU setup so variant without need of mutex would be required as well. Framebuffer setup code and other VideoCore calls check more precisely for errors and do not proceed forward with incorrect data now. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* bsp/qoriq: Remove legacy U-Boot supportSebastian Huber2016-07-289-208/+69
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* bsp/qoriq: Fix start stack setupSebastian Huber2016-07-281-3/+7
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* bsp/qoriq: Fix tlbwe synchronizationSebastian Huber2016-07-282-3/+5
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* bsp/qoriq: Add QORIQ_HAS_WRITE_BACK_L1_CACHESebastian Huber2016-07-272-0/+11
| | | | Fixes start via U-Boot on P1020.
* atsam: Add user defined RX/TX descriptor countsAlexander Krutwig2016-07-261-126/+102
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* atsam: Use normal memory for DTCMAlexander Krutwig2016-07-261-0/+1
| | | | Avoids problems with unaligned data access.
* bsps/arm: Clear pending exceptions for ARMv7-MAlexander Krutwig2016-07-261-0/+2
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* bsps: Fix shared polled console fatal errorSebastian Huber2016-07-252-1/+3
| | | | Fatal errors must uniquely identify the source location.
* arm/raspberrypi: add Secure Digital (SD) controller interrupt source ID from ↵Pavel Pisa2016-07-231-1/+1
| | | | Mudit Jain'a tree.
* arm/raspberrypi: change interrupt dispatch and enable to generic vector id ↵Pavel Pisa2016-07-232-141/+89
| | | | | | | | based approach. Using conditional branches to find bits is extremely inefficient and for asynchronous delivery of different interrupt sources lead to total confusion of branch prediction unit.
* arm/raspberrypi: remove duplicate setup of IRQ handler in the main ARM ↵Pavel Pisa2016-07-232-21/+0
| | | | | | | | | | | | | | | | | | | | | | | exception table. Exception table setup is processed by common CPU architecture support. For ARM architecture, it can be found in the file rtems/c/src/lib/libbsp/arm/shared/start/start.S and ends by bsp_vector_table_copy_done label. The actual tabel content can be found at bsp_start_vector_table_begin For ARMv7-A and even other variant with hypervisor mode support, it is even not necessary to copy table to address 0 at all because CP15 register can be used to specify alternative table start address arm_cp15_set_vector_base_address(&)bsp_start_vector_table_begin; ARMv7-M have register to set exception table base as well.
* Added USB interrupt handler. And defined some macros regarding USB.Deval Shah2016-07-233-0/+25
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* bsp/tms570: ensure that change of SCI baudrate is not applied in the middle ↵Pavel Pisa2016-07-221-2/+23
| | | | | | | | | | | | | | | | | of character Tx. The rtems_monitor_task() setups/updates termios attributes of the opened TTY and if there is ongoing some other output it leads to the stuck. It would be better to use some termios API function which would call drainOutput() in rtems/cpukit/libcsupport/src/termios.c. But functionality is not accessible outside of core termios implementation. The loop waiting for last character to be sent has to be there anyway because hardware does not provide Tx machine/shift register empty interrupt.
* arm/raspberrypi: reorder and update MMU config table to nor force RW section ↵Pavel Pisa2016-07-201-9/+22
| | | | | | | | | later to RO. Enable even the first megabyte of SDRAM to be cache-able after problems with stale cache content has been resolved by previous commit. Because major part of application usually fits to the first megabyte this speedups test dhrystone application by factor 40.
* arm/raspberrypi: use cache manager operations to flush/invalidate all cache ↵Pavel Pisa2016-07-201-7/+7
| | | | | | | | | levels. This fix strange behavior where some stale content has been stored in level 2 cache before RTEMS has been start from U-boot which has reappeared after MMU enable and shadow vector table at start of SDRAM.
* arm/bsps: CP15 and basic cache support entire cache clean for more ↵Pavel Pisa2016-07-203-6/+66
| | | | | | | | | | | | | | | | | architecture variants now. Next cache operations should work on most of cores now rtems_cache_flush_entire_data() rtems_cache_invalidate_entire_data() rtems_cache_invalidate_entire_instruction() Instruction cache invalidate works on the first level for now only. Data cacache operations are extended to ensure flush/invalidate on all cache levels. The CP15 arm_cp15_data_cache_clean_all_levels() function extended to continue through unified levels too (ctype = 4).
* bsps/arm: do not disable MMU during translation table management operations.Pavel Pisa2016-07-202-8/+58
| | | | | | | | | | | | | | | | | | | | Disabling MMU requires complex cache flushing and invalidation operations. There is almost no way how to do that right on SMP system without stopping all other CPUs. On the other hand, there is documented sequence of operations which should be used according to ARM manual and it guarantees even distribution of maintenance operations to other cores for last generation of Cortex-A cores with multiprocessor extension. This change could require addition of appropriate entry to arm_cp15_start_mmu_config_table for some BSPs to ensure that MMU table stays accessible after MMU is enabled { .begin = (uint32_t) bsp_translation_table_base, .end = (uint32_t) bsp_translation_table_base + 0x4000, .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED }
* arm/raspberrypi: cache manager can be used for mailbox synchronization now. ↵Pavel Pisa2016-07-201-33/+2
| | | | | | Remove workarounds. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* bsps/powerpc: Fix shared console driverSebastian Huber2016-07-191-13/+9
| | | | | | The Termios modes are now an emum. Do not use them in #if expressions. Close #2762.
* bsps/powerpc: Fix AtliVec context switchSebastian Huber2016-07-192-62/+68
| | | | | | | Properly pass the stack aligned context to _CPU_Context_switch_altivec() since _CPU_altivec_ctxt_off defined via ppc_context. Close #2761.
* beagle: pwm polishingPunit Vara2016-07-174-309/+568
| | | | | | | | | . added a README to pwm . added select_pwmss() to select pwmss-generic registers, as opposed to PWM-specific registers . added pwmss_clock_en_status(), beagle_pwmss_is_running() and pwmss_tb_clock_check() . other API improvements . style improvements
* Misc: Spell length correctlyJoel Sherrill2016-07-127-8/+8
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* bsps/powerpc: Fix AltiVec enableSebastian Huber2016-07-123-0/+3
| | | | | There must be an isync after the mtmsr to ensure that the AltiVec is enabled for subsequent instructions.
* shared/console-polled.c: Use standard fatal error codesJoel Sherrill2016-07-051-3/+3
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* bsps/arm: Fix basic cache support for SMPSebastian Huber2016-07-051-8/+8
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* Beaglebone: Update PWM driver imported from BBBIOPunit Vara2016-07-044-386/+611
| | | | | | This patch adapts the previously added Beaglebone PWM code from BBBIO to RTEMS. This work was done in the context of the Google Summer of Code 2016, and further patches will follow to improve the code quality and documentation.
* Beaglebone: Add original BBBIO PWM driverPunit Vara2016-07-042-0/+448
| | | | | | | | | This patch adds the PWM driver code for the Beaglebone Black from BBBIO: https://github.com/VegetableAvenger/BBBIOlib/blob/master/BBBio_lib/BBBiolib_PWMSS.c This commit is for tracking purposes only; the next commit will adapt the code for RTEMS.
* bsps/arm: basic on core cache support changed to use l1 functions.Pavel Pisa2016-07-043-48/+97
| | | | | | | | | | | | | | The basic data and instruction rage functions should be compatible for all ARMv4,5,6,7 functions. On the other hand, some functions are not portable, for example arm_cp15_data_cache_test_and_clean() and arm_cp15_data_cache_invalidate() for all versions and there has to be specialized version for newer cores. arm_cache_l1_properties_for_level uses CCSIDR which is not present on older chips. Actual version is only experimental, needs more changes and problem has been found on RPi1 with dlopen so there seems to be real problem.
* bsps/arm: Change code to explicit selection of cache implementation for ARM ↵Pavel Pisa2016-07-0410-124/+190
| | | | | | | | | | | | | | | | | | | | | | | BSPs. The original ARM architecture wide cache_.h is changed to dummy version for targets not implementing/enablig cache at all. The ARM targets equipped by cache should include appropriate implementation. Next options are available for now c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h basic ARM cache integrated on the CPU core directly which requires only CP15 oparations c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h support for case where ARM L2C-310 cache controller is used. It is accessible as mmaped peripheral. c/src/lib/libbsp/arm/shared/armv7m/include/cache_.h Cortex-M specific cache support
* bsp/arm: Report correct maximal cache line length for ARM Cortex-A + L2C-310.Pavel Pisa2016-07-041-0/+4
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* rtems+bsps/cache: Define cache manager operations for code synchronization ↵Pavel Pisa2016-07-041-0/+42
| | | | | | | | | | | | | | and maximal alignment. There is need for unambiguous named and defined cache function which should be called when code is updated, loaded or is self-modifying. There should be function to obtain maximal cache line length as well. This function can and should be used for allocations which can be used for data and or code and ensures that there are no partial cache lines overlaps on start and end of allocated region.
* arm/raspberrypi: update VideoCore cache flush workaround to work on RPi2.Pavel Pisa2016-07-041-2/+13
| | | | | The arm_cp15_data_cache_clean_and_invalidate leads to hang on RPi2, clean by individual lines works on RPi1 and RPi2.
* arm/raspberrypi: Enable HYP to SVC switch for this BSP.Pavel Pisa2016-07-042-0/+7
| | | | | This support is required when newer firmware is used on Raspberry Pi 2 boards.
* bsps/arm: Support recent bootloaders starting kernel in HYP modePavel Pisa2016-07-045-7/+175
| | | | | | | | | | | | | | | | | | | When HYP mode is detected at startup then setup HYP mode vectors table (for future extensions) clean exceptions switching to HYP mode and switch CPU to ARM SVC mode. BSPs which want to use this support need to include next option in their configure.ac RTEMS_BSPOPTS_SET([BSP_START_IN_HYP_SUPPORT],[*],[1]) RTEMS_BSPOPTS_HELP([BSP_START_IN_HYP_SUPPORT], [Support start of BSP in ARM HYP mode]) AM_CONDITIONAL(BSP_START_IN_HYP_SUPPORT,test "$BSP_START_IN_HYP_SUPPORT" = "1") and need to include next lines in corresponding Makefile.am if BSP_START_IN_HYP_SUPPORT libbsp_a_SOURCES += ../shared/startup/bsp-start-in-hyp-support.S endif
* arm/score and shared: define ARM hypervisor mode and alternate vector table ↵Pavel Pisa2016-07-041-0/+30
| | | | | | | | | base access. The main reason for inclusion of minimum hypervisor related defines is that current ARM boards firmware and loaders (U-boot for example) start loaded operating system kernel in HYP mode to allow it take control of virtualization (Linux/KVM for example).
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