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* Change all references of rtems.com to rtems.org.Chris Johns2014-03-211963-1982/+1982
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* libchip: Relax buffer counts and add fatal errorRalf Kirchner2014-03-142-3/+17
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* bsps/arm: Add DP83848 PHY support to LPC EthernetPavel Pisa2014-03-141-0/+8
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* bsps/arm: Add PHY detection to LPC EthernetPavel Pisa2014-03-141-13/+45
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* bsps/arm: Reset MII management in LPC EthernetPavel Pisa2014-03-141-1/+7
| | | | Reduce MII clock to support LPC17XX.
* bsp/lpc24xx: Add LPC24XX_PIN_ETHERNET_POWER_DOWNPavel Pisa2014-03-142-0/+15
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* bsp/lpc24xx: Add lpc24xx_pin_get_first_index()Sebastian Huber2014-03-141-0/+10
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* bsps/powerpc: Add support for interrupt profilingSebastian Huber2014-03-141-2/+51
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* bsps/leon3: Add interrupt delay profiling supportSebastian Huber2014-03-141-1/+38
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* sparc: Add support for interrupt profilingSebastian Huber2014-03-141-2/+23
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* score: Add SMP lock profiling supportSebastian Huber2014-03-141-1/+2
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* libchip: Include <bsp.h> BSP options definitionSebastian Huber2014-03-141-2/+2
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* libchip: Check interrupt extension availabilitySebastian Huber2014-03-131-0/+13
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* libchip: Avoid <bsp/utility.h>Sebastian Huber2014-03-132-578/+612
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* bsp/altera-cyclone-v: Made hwlib compile cleanRalf Kirchner2014-03-133-281/+6
| | | | Made Alteras hwlib compile clean within the RTEMS build system
* bsp/altera-cyclone-v: Add Alteras hwlibRalf Kirchner2014-03-1323-0/+71250
| | | | Add files from Alteras hwlib
* bsp/altera-cyclone-v: New BSPRalf Kirchner2014-03-1322-0/+2544
| | | | | | | | | | | | | Implemented so far: - nocache heap for uncached RAM - basic timer - level 1 cache handling for arm cache controller in arm-cache-l1.h - level 2 L2C-310 cache controller - MMU - DWMAC 1000 ethernet controller - basic errata handling - smp startup for second core
* libchip: Add dwmac 10/100/1000 network driverRalf Kirchner2014-03-1316-1/+6540
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* libbsp/xilinx-zynq: Share handling for ARM cache controller L2C-310Ralf Kirchner2014-03-133-988/+4
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* bsp/arm: Add handling for level 2 L2C-310 cache controllerRalf Kirchner2014-03-132-0/+1998
| | | | | | arm-l2c-310/cache_.h contains the handling for the L2C-310 level 2 cache controller from arm. It references the arm level 1 cache handling in the new file arm-cache-l1.h.
* bsp/arm: Add SCU errata handling for L2C-310 cacheRalf Kirchner2014-03-132-10/+36
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* bsp/xilinx-zynq: Add arm-errata.h and arm-release-id.hRalf Kirchner2014-03-132-0/+10
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* bsp/realview-pbx-a9: Add arm-errata.h and arm-release-id.hRalf Kirchner2014-03-132-0/+10
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* bsp/raspberrypi: Add arm-errata.h and arm-release-id.hRalf Kirchner2014-03-132-0/+10
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* bsp/lpc32xx: Add arm-errata.h and arm-release-id.hRalf Kirchner2014-03-132-0/+10
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* bsp/arm: Add arm-errata.h and arm-release-id.hRalf Kirchner2014-03-132-0/+279
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* bsp/arm: Add linker symbol bsp_processor_countRalf Kirchner2014-03-131-0/+2
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* bsp/arm: Add CP15 methodsRalf Kirchner2014-03-131-1/+98
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* bsp/arm: Separate setup for translation tableRalf Kirchner2014-03-131-4/+20
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* bsp/arm: Invalidate SCURalf Kirchner2014-03-132-1/+25
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* bsp/arm: SMP support for a9mpcore_clock_cleanup()Ralf Kirchner2014-03-131-4/+18
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* bsp/arm: Avoid warningRalf Kirchner2014-03-131-0/+1
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* bsps/powerpc: Fix GET_INTERRUPT_MASK macroSebastian Huber2014-03-121-1/+2
| | | | | Use _PPC_INTERRUPT_DISABLE_MASK introduced with 801b5d80325dbd3e92218271d54e75f389da7136.
* score: Add local context to SMP lock APISebastian Huber2014-03-111-16/+16
| | | | | | | | | | | Add a local context structure to the SMP lock API for acquire and release pairs. This context can be used to store the ISR level and profiling information. It may be later used to enable more sophisticated lock algorithms, e.g. MCS locks. There is only one lock that cannot be used with a local context. This is the per-CPU lock since here we would have to transfer the local context through a context switch which is very complicated.
* sapi: Use one SMP lock for all chainsSebastian Huber2014-03-112-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This partially reverts commit 1215fd4d9426a59d568560e9a485628560363133. In order to support profiling of SMP locks and provide a future compatible SMP locks API it is necessary to add an SMP lock destroy function. Since the commit above adds an SMP lock to each chain control we would have to add a rtems_chain_destroy() function as well. This complicates the chain usage dramatically. Thus revert the patch above. A global SMP lock for all chains is used to implement the protected chain operations. Advantages: * The SAPI chain API is now identical on SMP and non-SMP configurations. * The size of the chain control is reduced and is then equal to the Score chains. * The protected chain operations work correctly on SMP. Disadvantage: * Applications using many different chains and the protected operations may notice lock contention. The chain control size drop is a huge benefit (SAPI chain controls are 66% larger than the Score chain controls). The only disadvantage is not really a problem since these applications can use specific interrupt locks and unprotected chain operations to avoid this issue.
* bsp/leon3: Use interrupt timestamping counterSebastian Huber2014-03-102-28/+73
| | | | | Use the interrupt controller timestamping counter for the CPU counter if available since it runs with a high frequency.
* bsps/sparc: Add missing IRQMP registersSebastian Huber2014-03-101-3/+13
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* bsps/sparc: Remove fix for ERC32 with FPU rev. B/CSebastian Huber2014-03-101-66/+0
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* rtems: Add RTEMS_INTERRUPT_REPLACESebastian Huber2014-03-061-27/+54
| | | | | | | | | | | | | | | | | | | | | A new option RTEMS_INTERRUPT_REPLACE is introduced that permits updating the first interrupt handler for the registered interrupt vector and matching argument. If no match is found, the install function fails with RTEMS_UNSATISFIED. The Interrupt Manager Extension offers interrupt handlers with an argument pointer. It is impossible to update two words (handler and argument) atomically on most architectures. In order to avoid an SMP lock in bsp_interrupt_handler_dispatch() which would degrade the interrupt response time an alternative must be provided that makes it possible to tear-down interrupt sources without an SMP lock. Add RTEMS_INTERRUPT_REPLACE option to Interrupt Manager Extension. This enables a clean tear-down of interrupt sources on SMP configurations. Instead of an interrupt handler removal a replacement handler can be installed to silence an interrupt source. This can be used in contexts that allow no sophisticated synchronization (e.g. in atexit() or fatal handlers).
* bsps: SMP support for generic interrupt supportSebastian Huber2014-03-062-18/+59
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* bsp/leon3: Unmask IPI only on secondary processorDaniel Hellstrom2014-03-061-1/+1
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* bsp/leon3: Add L2 cache supportSebastian Huber2014-02-281-0/+88
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* bsp/leon3: Add L2C registersSebastian Huber2014-02-281-0/+25
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* bsp/leon3: Add new cache manager implementationSebastian Huber2014-02-282-1/+114
| | | | | | | | | | | The previous implementation used an instruction cache line size of 0, this is a bogus value. Use a instruction cache line size of 64 since the L2 cache may have a line size of 32 or 64. A greater value should cause no harm. Use a FLUSH operation for _CPU_cache_invalidate_instruction_range(). This is a preperation step to support the L2 cache.
* bsp/leon3: Add and use cache register functionsSebastian Huber2014-02-283-21/+46
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* rtems: Add cache size functionsSebastian Huber2014-02-281-0/+21
| | | | | Add rtems_cache_get_data_cache_size() and rtems_cache_get_instruction_cache_size().
* rtems: Use size_t for cache line sizeSebastian Huber2014-02-283-4/+4
| | | | A cache line cannot have a negative size.
* bsp/leon3: Use ambapp_freq_get() for CPU counterSebastian Huber2014-02-283-40/+33
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* bsps: Delete LEON3_FATAL_CPU_COUNTER_INITSebastian Huber2014-02-281-2/+1
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* bsps: Fix empty interrupt handler entrySebastian Huber2014-02-281-4/+5
| | | | | The vector number of spurious interrupts was wrong after the interrupt handler removal on SMP configurations.