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* score/sparc: Add support for paravirtualizationChristian Mauderer2014-06-036-1/+76
| | | | | | | Guest systems in paravirtualization environments run usually in user mode. Thus it is not possible to directly access the PSR and TBR registers. Use functions instead of inline assembler to access these registers if RTEMS_PARAVIRT is defined.
* mrm332: Tests now build and fewer warningsJoel Sherrill2014-06-014-12/+10
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* m68k/shared/misc/memProbe.c: Add prototype to eliminate warningJoel Sherrill2014-06-011-0/+2
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* bsps/gdbarmsim: Add the missing bspstarthooks.c.Chris Johns2014-05-301-0/+20
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* SPARC: syscall optimizations and PSR-write fixDaniel Hellstrom2014-05-282-15/+24
| | | | | | | | | | | | | | | The last optimization missed was incorrect in regards to PSR write instruction delay must be 3 instructions. New optimizations: * align to 32-byte cache line. * rearrange code into three "blocks" of 4 instructions that is executed by syscall 2 and 3. This is to optimize for 16/32 byte cache lines. * use delay-slot instruction in trap table to reduce by one instruction. * use the fact that "wr %PSR" implements XOR to reduce by one instruction.
* LEON3: coding style clean bsp_irq_fixup()Daniel Hellstrom2014-05-281-9/+9
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* LEON3: add support for IRQ16..31 for CPU!=0Daniel Hellstrom2014-05-281-2/+3
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* bsps: Do not build tests that require a tick interrupt.Chris Johns2014-05-2821-0/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following BSPs do not have tick support so the tests fail: arm1136jfs arm1136js arm7tdmi arm920 armcortexa9 (does not run any more) avrtest h8sim h8sxsim m32csim m32rsim moxiesim simsh1 simsh2 simsh4 v850e1sim v850e2sim v850e2v3sim v850esim v850essim v850sim This list was provided by Joel in the following post: http://www.rtems.org/pipermail/rtems-devel/2014-April/006526.html
* bsp/altera-cyclone-v: CleanupRalf Kirchner2014-05-281-3/+3
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* bsp/altera-cyclone-v: Reduce size of nocache heapRalf Kirchner2014-05-282-4/+4
| | | | Network mbufs and clusters now are cached. Thus the nocache heap can get reduced to 1 MByte.
* bsp/altera-cyclone-v: Cache mbufs and clustersRalf Kirchner2014-05-281-12/+0
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* bsp/altera-cyclone-v: Enable L2 cache for network driverRalf Kirchner2014-05-281-1/+14
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* bsp/altera-vyclone-v: Broadcast cache maintenancesRalf Kirchner2014-05-281-3/+3
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* bsp/arm: Broadcast cache maintenancesRalf Kirchner2014-05-281-1/+1
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* bsps/sparc: Change tabs to spaces.Daniel Cederman2014-05-2718-311/+309
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* bsps/sparc: Add copyright and license informationDaniel Cederman2014-05-2720-38/+157
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* bsps/sparc: Make lines in SPARC BSPs adhere to 80 character limit.Daniel Cederman2014-05-2721-183/+292
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* bsp/gdbarmsim: Switch to the standard arm/shared/startup.Chris Johns2014-05-265-402/+143
| | | | | | | Switch to the standard ARM startup code. This requires adding the standard interrupt code. The interrupt code does nothing at this point in time. I do not know if the ARM simulator in GDB supports interrupts.
* bsp/gdbarmsim: Change syscall functions to not clash with RTEMS functions.Chris Johns2014-05-263-175/+104
| | | | | | | | | | | | The syscall functions overlapped with RTEMS, for example _write, _read, etc. Change these to be internal to the BSP and avoid any clash with names in RTEMS. Add support for SWI_Write0. Change the console driver to use SWI_Write0. This outputs the character to the host's stdout. Writing to file name 0 is not captured and managed by GDB's simulation code while the SWI_Write0 is. The managed stdout data is encapulated in the MI protocol while writes to file handle 0 are dropped by GDB when in MI mode.
* SPARC: add syscall 1 (exit) function entry pointDaniel Hellstrom2014-05-231-0/+13
| | | | | | The exit SPARC system call doesn't have a function entry point like the others do. This is probably why people use TA 0x0 instruction directly for shutting down the system.
* SPARC: syscall code clean-up and minor optimizationsDaniel Hellstrom2014-05-231-16/+11
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* c/src/aclocal/check-smp.m4: Use HAS_SMP not HAS_POSIX_APIJoel Sherrill2014-05-221-1/+1
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* bsp/zynq: Add BSP_ZYNQ_RAM_LENGTH to allow a user to override the RAM length.Chris Johns2014-05-221-10/+13
| | | | | The Zynq BSPs can be used with varations of hardware such as memory size. This option lets you set a length.
* bsps/zynq: Add BSP_ARM_A9MPCORE_UARTCLK to set the UART clock rate.Chris Johns2014-05-222-1/+8
| | | | | This value can be found the xparameters.h file generated by the Xilinx tools.
* bsps/sparc: Fix BSS initializationSebastian Huber2014-05-141-2/+0
| | | | | | | | Use __bss_start available via %g2 to clear the BSS section. The usage of _edata resulted in a copy of [_edata, __bss_start) from ROM to RAM and then a clear to zero of this area. Clear now only [__bss_start, _end).
* bsps/sparc: Fix data copy in start procedureSebastian Huber2014-05-141-9/+9
| | | | | | Use the register %g4 for the data content since it must be an even numbered register due to the std/ldd. Use the register %g2 for the BSS start address, so that it can be later re-used for the BSS zero loop.
* bsp/altera-caclone-v: Early printk supportRalf Kirchner2014-05-121-24/+4
| | | | Make sure printk can work early during BSP startup.
* bsps: Declare bsp_start_on_secondary_processors()Sebastian Huber2014-05-121-1/+11
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* bsps: Use bsp_start_on_secondary_processor()Sebastian Huber2014-05-126-14/+9
| | | | Use a standard function for startup on secondary processors.
* bsps: Use standard file name for BSP supportSebastian Huber2014-05-129-28/+13
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* bsp/leon3: Delete unused functionSebastian Huber2014-05-121-5/+0
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* bsps/sparc: Move flags to grlib headerChristian Mauderer2014-05-125-10/+14
| | | | This enables re-use for other BSPs
* bsp/gen83xx: Disable interrupt nesting for br_uidSebastian Huber2014-05-081-2/+3
| | | | This is necessary for the USB support.
* score: Fix CPU context usage on SMPSebastian Huber2014-05-083-17/+9
| | | | | | | | | | We must not alter the is executing indicator in _CPU_Context_Initialize() since this would cause an invalid state during a self restart. The is executing indicator must be valid at creation time since otherwise _Thread_Kill_zombies() uses an undefined value for not started threads. This could result in a system life lock.
* score: Implement forced thread migrationSebastian Huber2014-05-073-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current implementation of task migration in RTEMS has some implications with respect to the interrupt latency. It is crucial to preserve the system invariant that a task can execute on at most one processor in the system at a time. This is accomplished with a boolean indicator in the task context. The processor architecture specific low-level task context switch code will mark that a task context is no longer executing and waits that the heir context stopped execution before it restores the heir context and resumes execution of the heir task. So there is one point in time in which a processor is without a task. This is essential to avoid cyclic dependencies in case multiple tasks migrate at once. Otherwise some supervising entity is necessary to prevent life-locks. Such a global supervisor would lead to scalability problems so this approach is not used. Currently the thread dispatch is performed with interrupts disabled. So in case the heir task is currently executing on another processor then this prolongs the time of disabled interrupts since one processor has to wait for another processor to make progress. It is difficult to avoid this issue with the interrupt latency since interrupts normally store the context of the interrupted task on its stack. In case a task is marked as not executing we must not use its task stack to store such an interrupt context. We cannot use the heir stack before it stopped execution on another processor. So if we enable interrupts during this transition we have to provide an alternative task independent stack for this time frame. This issue needs further investigation.
* bsps/arm: Declare return typesSebastian Huber2014-05-071-7/+8
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* bsps: Fix BSP_INITIAL_EXTENSIONSebastian Huber2014-05-071-1/+1
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* multiple BSPs: Remove BSP_SMALL_MEMORYJoel Sherrill2014-05-0614-35/+0
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* bsp/gen83xx: Add BSP_USB_EHCI_MPC83XX_HAS_ULPISebastian Huber2014-05-061-0/+3
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* testsuite: Add a per BSP test check for tests not to build.Chris Johns2014-05-0530-0/+416
| | | | | | | | Provide a file per BSP to list tests that do not build for a BSP. This change removes the BSP_SMALL_MEMORY hack from the code. That hack was a mistake. Provide configuration files for each BSP with tests that cannot build.
* libchip: Add asserts to dwmac driverRalf Kirchner2014-04-301-0/+3
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* libchip: Correct netstats message for dwmac driverRalf Kirchner2014-04-301-1/+1
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* bsp/altera-cyclone-v: Move mbufs and network clusters to uncached RAMRalf Kirchner2014-04-301-0/+12
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* bsp/altera-cyclone-v: Increase size of nocache region and nocache heapRalf Kirchner2014-04-302-3/+3
| | | | Increase size of nocache heap in order to be able to move mbufs and clusters of the network driver to uncached RAM
* score: Statically initialize _ISR_Vector_tableSebastian Huber2014-04-293-3/+1
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* bsps/mips: Delete unused filesSebastian Huber2014-04-2915-705/+0
| | | | The MIPS port defines CPU_SIMPLE_VECTORED_INTERRUPTS to FALSE.
* bsps/m32r: Fix bsp_specsSebastian Huber2014-04-291-6/+4
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* bsps/bfin: Fix bsp_specsSebastian Huber2014-04-295-25/+12
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* bsp/h8sim: Fix linker command fileSebastian Huber2014-04-291-0/+2
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* sparc: Add _CPU_Get_current_per_CPU_control()Sebastian Huber2014-04-282-60/+33
| | | | | | | | | | | | | | | | Use register g6 for the per-CPU control of the current processor. The register g6 is reserved for the operating system by the SPARC ABI. On Linux register g6 is used for a similar purpose with the same method since 1996. The register g6 must be initialized during system startup and then must remain unchanged. Since the per-CPU control is used in all critical sections of the operating system, this is a performance optimization for the operating system core procedures. An additional benefit is that the low-level context switch and interrupt processing code is now identical on non-SMP and SMP configurations.
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