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* classic networking: do not reference BSP_irq_enabled_at_i8259s which is no ↵Pavel Pisa2016-09-205-40/+5
| | | | | | | more available on i386. This change is required to build RTEMS with classic "--enable-networking" and link applications/tests which reference RTEMS_BSP_NETWORK_DRIVER_ATTACH.
* termios: Use IMFS nodes for new Termios devicesSebastian Huber2016-09-197-83/+21
| | | | | | | | This makes the new Termios devices independent of device major/minor numbers. It enables BSP independent Termios device drivers which may reside in the cpukit domain. These drivers require an IMFS and do not work with the device file system. However, the device file system should go away in the future.
* bsp/atsam: Add SPI bus driverAlexander Krutwig2016-09-166-0/+770
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* bsp/atsam: Use normal memory for QSPI flash areaAlexander Krutwig2016-09-161-2/+2
| | | | This is a performance improvement for execute-in-place (XIP).
* arm/raspberrypi: define bsp_reset to restart board by watchdog.Pavel Pisa2016-09-083-1/+82
| | | | | Whether the board is restarted after application finish/exit is controlled by BSP_RESET_BOARD_AT_EXIT configure option.
* powerpc: Fix SMP context switchSebastian Huber2016-09-081-61/+62
| | | | | | We need the unmodified r4 for get_potential_new_heir. This partially reverts commit 8d785f72d9610fb80a65d7848404f0f7507e026c.
* testsuite: Add libdl/dl05 reloc test.Chris Johns2016-09-083-0/+3
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* bsp/raspberrypi: Rename fileSebastian Huber2016-09-082-1/+1
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* arm/raspberrypi: use GPU/system timer as clock source.Pavel Pisa2016-09-071-36/+62
| | | | | | It has advantage that it is designed as free-running counter with compare registers and can easily serve for for both timecounter and tick interrupt.
* arm/raspberrypi: correct and extend definitions for GPU timer.Pavel Pisa2016-09-072-7/+16
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* arm/raspberrypi: basic BCM2836 SMP implementation.Pavel Pisa2016-09-078-4/+230
| | | | | | | | The BSP support is divided to startup/bspsmp_api.c file where functions required by SuperCore are defined and BCM2836 hardware initialization part in startup/bspsmp_init.c. Separation is done to prevent smpfatal08 test build failure.
* arm/raspberrypi: propagate number of configured CPUs into linker script.Pavel Pisa2016-09-072-0/+16
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* arm/raspberrypi: rename linkcmds to linkcmds.in to allow their configure ↵Pavel Pisa2016-09-073-4/+3
| | | | processing.
* arm/raspberrypi: more definitions of BCM2836 core local peripherals.Pavel Pisa2016-09-071-2/+140
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* arm/raspberrypi: include definitions of BCM2836 SMP mailboxes.Rohini Kulkarni2016-09-071-0/+26
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* bsps/arm: reorganize CP15 code to allow clean and invalidate ARMv7 cache by ↵Pavel Pisa2016-09-071-48/+60
| | | | | | | level. New function arm_cp15_cache_invalidate_level and arm_cp15_cache_clean_level can be used to maintain single cache level (instruction or data).
* bsps/arm: remove lock in arm_cp15_set_translation_table_entries().Pavel Pisa2016-09-071-9/+1
| | | | | | | | | | | Protection by rtems_interrupt_disable() is incompatible with SMP build. Actual page table entries manipulation function does not need locking and disabling cache and can be run concurrently even on multiple CPUs as long as changes do not modify same region. If the function is called from more threads/CPUs to modify same region with different mapping options concurrently then there is problem at another level of virtual address space management and has to be solved by mutex or other locking at that level.
* bsps/arm: use defines for cache type register format field.Pavel Pisa2016-09-071-9/+30
| | | | | | The change documents meaning of codes and opens well defined way to use cache type format for cache examination/debugging outside of arm-cp15.h file.
* bsp/atsam: Add SDRAM IS42S16320F-7BL.Christian Mauderer2016-09-073-1/+56
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* bsp/atsam: Move ram init values to structure.Christian Mauderer2016-09-074-0/+58
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* bsp/xilinx-zynq: Avoid duplicate declarationSebastian Huber2016-09-061-1/+1
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* arm/xilinx_zynq: Start the second core when an SMP build.Chris Johns2016-09-012-0/+22
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* arm/xilinx_zynq: ensure that cache is cleaned and MMU disabled when ↵Pavel Pisa2016-09-011-0/+35
| | | | | | | | | initialization starts. The u-boot loader enables the MMU plus the data and instruction caches in some versions which results in RTEMS boot failure. Closes #2774.
* libdl: The dl04 is too big for some BSPs. Do not built it.Chris Johns2016-08-303-0/+3
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* arm/raspberrypi: Mailbox : Extending functionalityMudit Jain2016-08-273-0/+130
| | | | | Adding functionality to get board serial, power state & clock rate
* bsp/atsam: Add missing break statementAlexander Krutwig2016-08-241-0/+1
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* bsp/atsam: Fix data cache flushAlexander Krutwig2016-08-241-3/+7
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* libbsp/arm: Fix ARM BSPs missing the bsp_translation_table_end symbol.Chris Johns2016-08-232-0/+2
| | | | Closes #2775.
* bsp/atsam: Add timeout to QSPI send commandAlexander Krutwig2016-08-181-1/+16
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* libbsp/arm: Add the TTB table to the default MMU set up as read/write.Chris Johns2016-08-151-0/+4
| | | | | | | This lets the table be changed at runtime for dynamic loading and debugger support. Closes #2775.
* librtems++: Remove from RTEMS.Chris Johns2016-08-1120-2462/+0
| | | | | | | This is old and there are better design patterns for threading and C++. We recommend you use the new C++ standards based support. Closes #2777.
* build-system: Always enable C++ if the compiler is present.Chris Johns2016-08-113-18/+26
| | | | | | | | | | | We always build a C++ compiler and building with C++ does not effect RTEMS or the runtime. This patch always enabled the support. There is no need to manually enable it any more. You can disable C++ with '--disable-cxx'. If an architecture does not have a C++ compiler support is automatically disabled.
* bsp/atsam: Add power supportAlexander Krutwig2016-08-087-0/+505
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* atsam: Add atsam_rtc_get_time()Alexander Krutwig2016-08-082-16/+23
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* arm/raspberrypi: framebuffer driver checks for initialization and tries ↵Pavel Pisa2016-07-311-1/+11
| | | | | | | | | | | | | | | runtime init if required. Code works but there is problem how to setup caching for the regions (arm_cp15_set_translation_table_entries arguments). If ARMV7_MMU_DATA_READ_WRITE_CACHED is used then CPU accesses are noncoherent with VideoCore and some part of image update are not visible until pushed from cache by other activities. If ARMV7_MMU_DATA_READ_WRITE is used then access is extremely slow. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* arm/raspberrypi: VideoCore access corrections in cache operation and more ↵Pavel Pisa2016-07-316-48/+112
| | | | | | | | | | | | | | | | | | | | | | | | | | | | error checking. The first, mistake in buffer size computation for cache flush and invalidate has been corrected. GCC __attribute__( ( aligned( 64 ) ) ) should work and works for local variables. Code ensures right stack alignment. But attribute has to be moved to type declaration to ensure that structure size is affected by attribute. But even this seems to not work reliably for some reason. May it be, the stack area between frame start and end of local variable buffer accessed during context switch or some stack prefetch during resturn such way that some cache lines belonging to buffer are filled to cache. Extending buffer by one more cache line padding helps there. In the longer term perspective, buffer should be moved to some static area or cache aligned dynamic memory allocated. Concurrent calls to the VideoCore operations and access serialization should be added too but problem is that some calls are required during workspace and MMU setup so variant without need of mutex would be required as well. Framebuffer setup code and other VideoCore calls check more precisely for errors and do not proceed forward with incorrect data now. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* bsp/qoriq: Remove legacy U-Boot supportSebastian Huber2016-07-289-208/+69
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* bsp/qoriq: Fix start stack setupSebastian Huber2016-07-281-3/+7
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* bsp/qoriq: Fix tlbwe synchronizationSebastian Huber2016-07-282-3/+5
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* bsp/qoriq: Add QORIQ_HAS_WRITE_BACK_L1_CACHESebastian Huber2016-07-272-0/+11
| | | | Fixes start via U-Boot on P1020.
* atsam: Add user defined RX/TX descriptor countsAlexander Krutwig2016-07-261-126/+102
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* atsam: Use normal memory for DTCMAlexander Krutwig2016-07-261-0/+1
| | | | Avoids problems with unaligned data access.
* bsps/arm: Clear pending exceptions for ARMv7-MAlexander Krutwig2016-07-261-0/+2
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* bsps: Fix shared polled console fatal errorSebastian Huber2016-07-252-1/+3
| | | | Fatal errors must uniquely identify the source location.
* arm/raspberrypi: add Secure Digital (SD) controller interrupt source ID from ↵Pavel Pisa2016-07-231-1/+1
| | | | Mudit Jain'a tree.
* arm/raspberrypi: change interrupt dispatch and enable to generic vector id ↵Pavel Pisa2016-07-232-141/+89
| | | | | | | | based approach. Using conditional branches to find bits is extremely inefficient and for asynchronous delivery of different interrupt sources lead to total confusion of branch prediction unit.
* arm/raspberrypi: remove duplicate setup of IRQ handler in the main ARM ↵Pavel Pisa2016-07-232-21/+0
| | | | | | | | | | | | | | | | | | | | | | | exception table. Exception table setup is processed by common CPU architecture support. For ARM architecture, it can be found in the file rtems/c/src/lib/libbsp/arm/shared/start/start.S and ends by bsp_vector_table_copy_done label. The actual tabel content can be found at bsp_start_vector_table_begin For ARMv7-A and even other variant with hypervisor mode support, it is even not necessary to copy table to address 0 at all because CP15 register can be used to specify alternative table start address arm_cp15_set_vector_base_address(&)bsp_start_vector_table_begin; ARMv7-M have register to set exception table base as well.
* Added USB interrupt handler. And defined some macros regarding USB.Deval Shah2016-07-233-0/+25
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* bsp/tms570: ensure that change of SCI baudrate is not applied in the middle ↵Pavel Pisa2016-07-221-2/+23
| | | | | | | | | | | | | | | | | of character Tx. The rtems_monitor_task() setups/updates termios attributes of the opened TTY and if there is ongoing some other output it leads to the stuck. It would be better to use some termios API function which would call drainOutput() in rtems/cpukit/libcsupport/src/termios.c. But functionality is not accessible outside of core termios implementation. The loop waiting for last character to be sent has to be there anyway because hardware does not provide Tx machine/shift register empty interrupt.
* arm/raspberrypi: reorder and update MMU config table to nor force RW section ↵Pavel Pisa2016-07-201-9/+22
| | | | | | | | | later to RO. Enable even the first megabyte of SDRAM to be cache-able after problems with stale cache content has been resolved by previous commit. Because major part of application usually fits to the first megabyte this speedups test dhrystone application by factor 40.
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