| Commit message (Collapse) | Author | Age | Files | Lines |
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Update #3090.
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Update #3090.
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Update #3090.
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Make Clock_driver_support_shutdown_hardware() optional. This avoids
the atexit() support on memory constrained targets.
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Use a specific define for the interrupt exception frame size.
Update #3082.
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Rename ppc_exc_wrap_async_normal to ppc_exc_interrupt to avoid a bit of
obfuscation.
Update #3082.
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There is no need to explicitly set the output format and architecture in
the linker script. This enables the usage of this linker script with
the ELFv2 ABI (64-bit).
Update #3082.
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Avoid use of small-data area, since it is not supported in the ELFv2 ABI
by GCC.
Update #3082.
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Intel has obsoleted this hardware and the BSP was never completed.
closes #3086.
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Update #3082.
Update #3085.
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Due to the FDT support we can now reduce the BSP variants. Use the
processor core to define the BSP variants.
Update #3082.
Update #3085.
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Do not flush/invalidate the caches. Instead enable the cache during the
low-level initialization and perform an explicit cache flush for the
read-only and fast-text sections.
Update #3082.
Update #3085.
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The SPARC ABI is a bit special with respect to the floating point context.
The complete floating point context is volatile. Thus, from an ABI point
of view nothing needs to be saved and restored during a context switch.
Instead the floating point context must be saved and restored during
interrupt processing. Historically, the deferred floating point switch was
used for SPARC and the complete floating point context is saved and
restored during a context switch to the new floating point unit owner.
This is a bit dangerous since post-switch actions (e.g. signal handlers)
and context switch extensions may silently corrupt the floating point
context.
The floating point unit is disabled for interrupt handlers. Thus, in case
an interrupt handler uses the floating point unit then this will result in a
trap (INTERNAL_ERROR_ILLEGAL_USE_OF_FLOATING_POINT_UNIT).
In uniprocessor configurations, a lazy floating point context switch is
used. In case an active floating point thread is interrupted (PSR[EF] == 1)
and a thread dispatch is carried out, then this thread is registered as the
floating point owner. When a floating point owner is present during a
context switch, the floating point unit is disabled for the heir thread
(PSR[EF] == 0). The floating point disabled trap checks that the use of the
floating point unit is allowed and saves/restores the floating point context
on demand.
Update #3077.
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Add new fatal error INTERNAL_ERROR_ILLEGAL_USE_OF_FLOATING_POINT_UNIT.
Update #3077.
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Rename SPARC_USE_SAFE_FP_SUPPORT in SPARC_USE_SYNCHRONOUS_FP_SWITCH.
Update comment.
Update #3077.
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Fix infinite loop in rtems_invalidate_multiple_instruction_lines().
Implement this function.
Close #3080.
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Update #3071.
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Rename NGMP to GR740 and add configs for UT699, UT700, and GR712RC
The UT699 requires -mcpu=leon as it does not support the CAS instruction
provided by -mcpu=leon3. It also requires -mfix-ut699 for errata fixes.
UT700 and GR712RC requires the -mfix-ut700 and -mfix-gr712rc flags that
have been recently added to GCC's master and 7-branch.
Remove -msoft-float from the leon3 config to make the more common case
of using the FPU the default.
Update #3057.
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This patch adds NOP instructions to prevent instruction sequences
that are sensitive to the LEON3FT B2BST errata. See GRLIB-TN-0009:
"LEON3FT Stale Cache Entry After Store with Data Tag Parity Error"
for more information.
The sequences are only modified if __FIX_LEON3FT_B2BST is defined.
The patch works in conjunction with the -mfix-ut700, -mfix-gr712rc,
and -mfix-ut699 GCC flags that prevents the sensitive sequences from
being generated.
Update #3057.
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Update #3071.
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Close #3071.
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Update #3071.
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Update #3071.
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This mechanism can be used to safely move the interrupt server from one
scheduler instance to another for example.
Update #3071.
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This allows load balancing of interrupt processing in SMP
configurations.
Update #3071.
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Update #3059.
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Update #3059.
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Implement the Processor_mask via <sys/bitset.h>. Provide
_Processor_mask_To_uint32_t() to enable its use in device specific
routines, e.g. interrupt affinity register in an interrupt controller.
Update #3059.
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Change bsp_interrupt_vector_enable() and bsp_interrupt_vector_disable()
to not return a status code. Add bsp_interrupt_assert() and use it to
validate the vector number in the vector enable/disable implementations.
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Close #3051.
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Update ticket #2891 and my GSOC project
add c/src/lib/libbsp/arm/beagle/i2c/bbb-i2c.c
modify c/src/lib/libbsp/arm/beagle/include/i2c.h
modify c/src/lib/libbsp/arm/beagle/include/bbb-gpio.h
modify c/src/lib/libcpu/arm/shared/include/am335x.h
modify c/src/lib/libbsp/arm/beagle/Makefile.am
Now can read the EEPROM by i2c, the test application link is: https://github.com/hahchenchen/GSOC-test-application
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modify c/src/lib/libbsp/arm/beagle/Makefile.am
modify c/src/lib/libbsp/arm/beagle/include/i2c.h
delete c/src/lib/libbsp/arm/beagle/misc/i2c.c
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According to manual, the used operations (Clean Line by PA, Clean and
Invalidate Line by PA, Cache Sync) are atomic and do not require
locking.
Update #3007.
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