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* score: Add local context to SMP lock APISebastian Huber2014-03-111-16/+16
| | | | | | | | | | | Add a local context structure to the SMP lock API for acquire and release pairs. This context can be used to store the ISR level and profiling information. It may be later used to enable more sophisticated lock algorithms, e.g. MCS locks. There is only one lock that cannot be used with a local context. This is the per-CPU lock since here we would have to transfer the local context through a context switch which is very complicated.
* sapi: Use one SMP lock for all chainsSebastian Huber2014-03-112-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This partially reverts commit 1215fd4d9426a59d568560e9a485628560363133. In order to support profiling of SMP locks and provide a future compatible SMP locks API it is necessary to add an SMP lock destroy function. Since the commit above adds an SMP lock to each chain control we would have to add a rtems_chain_destroy() function as well. This complicates the chain usage dramatically. Thus revert the patch above. A global SMP lock for all chains is used to implement the protected chain operations. Advantages: * The SAPI chain API is now identical on SMP and non-SMP configurations. * The size of the chain control is reduced and is then equal to the Score chains. * The protected chain operations work correctly on SMP. Disadvantage: * Applications using many different chains and the protected operations may notice lock contention. The chain control size drop is a huge benefit (SAPI chain controls are 66% larger than the Score chain controls). The only disadvantage is not really a problem since these applications can use specific interrupt locks and unprotected chain operations to avoid this issue.
* bsp/leon3: Use interrupt timestamping counterSebastian Huber2014-03-102-28/+73
| | | | | Use the interrupt controller timestamping counter for the CPU counter if available since it runs with a high frequency.
* bsps/sparc: Add missing IRQMP registersSebastian Huber2014-03-101-3/+13
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* bsps/sparc: Remove fix for ERC32 with FPU rev. B/CSebastian Huber2014-03-101-66/+0
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* rtems: Add RTEMS_INTERRUPT_REPLACESebastian Huber2014-03-061-27/+54
| | | | | | | | | | | | | | | | | | | | | A new option RTEMS_INTERRUPT_REPLACE is introduced that permits updating the first interrupt handler for the registered interrupt vector and matching argument. If no match is found, the install function fails with RTEMS_UNSATISFIED. The Interrupt Manager Extension offers interrupt handlers with an argument pointer. It is impossible to update two words (handler and argument) atomically on most architectures. In order to avoid an SMP lock in bsp_interrupt_handler_dispatch() which would degrade the interrupt response time an alternative must be provided that makes it possible to tear-down interrupt sources without an SMP lock. Add RTEMS_INTERRUPT_REPLACE option to Interrupt Manager Extension. This enables a clean tear-down of interrupt sources on SMP configurations. Instead of an interrupt handler removal a replacement handler can be installed to silence an interrupt source. This can be used in contexts that allow no sophisticated synchronization (e.g. in atexit() or fatal handlers).
* bsps: SMP support for generic interrupt supportSebastian Huber2014-03-062-18/+59
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* bsp/leon3: Unmask IPI only on secondary processorDaniel Hellstrom2014-03-061-1/+1
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* bsp/leon3: Add L2 cache supportSebastian Huber2014-02-281-0/+88
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* bsp/leon3: Add L2C registersSebastian Huber2014-02-281-0/+25
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* bsp/leon3: Add new cache manager implementationSebastian Huber2014-02-282-1/+114
| | | | | | | | | | | The previous implementation used an instruction cache line size of 0, this is a bogus value. Use a instruction cache line size of 64 since the L2 cache may have a line size of 32 or 64. A greater value should cause no harm. Use a FLUSH operation for _CPU_cache_invalidate_instruction_range(). This is a preperation step to support the L2 cache.
* bsp/leon3: Add and use cache register functionsSebastian Huber2014-02-283-21/+46
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* rtems: Add cache size functionsSebastian Huber2014-02-281-0/+21
| | | | | Add rtems_cache_get_data_cache_size() and rtems_cache_get_instruction_cache_size().
* rtems: Use size_t for cache line sizeSebastian Huber2014-02-283-4/+4
| | | | A cache line cannot have a negative size.
* bsp/leon3: Use ambapp_freq_get() for CPU counterSebastian Huber2014-02-283-40/+33
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* bsps: Delete LEON3_FATAL_CPU_COUNTER_INITSebastian Huber2014-02-281-2/+1
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* bsps: Fix empty interrupt handler entrySebastian Huber2014-02-281-4/+5
| | | | | The vector number of spurious interrupts was wrong after the interrupt handler removal on SMP configurations.
* sparc: Fix CPU counter supportSebastian Huber2014-02-246-36/+96
| | | | | | | | The SPARC processors supported by RTEMS have no built-in CPU counter support. We have to use some hardware counter module for this purpose. The BSP must provide a 32-bit register which contains the current CPU counter value and a function for the difference calculation. It can use for example the GPTIMER instance used for the clock driver.
* bsps: Add empty cache managerSebastian Huber2014-02-2421-1/+98
| | | | | This is necessary to add tests that use the cache manager. For example to get better estimates of worst-case timings.
* bsps/powerpc: Use System V small-data areaSebastian Huber2014-02-248-8/+8
| | | | | | The 32-bit ABIs for thread-local storage (TLS) and EABI read-only small-data area have a conflicting register (r2) usage. Use the System V small-data instead (here r2 is system reserved).
* bsp/leon3: Add bsp_reset() for SMP configurationSebastian Huber2014-02-213-0/+65
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* bsp/leon3: Add and use leon3_get_cpu_count()Sebastian Huber2014-02-212-2/+10
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* bsp/leon3: Add leon3_power_down_loop()Sebastian Huber2014-02-212-0/+4
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* bsps/sparc: Delete unused fileSebastian Huber2014-02-211-24/+0
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* bsp/score603e: Remove unused BSP_fatal_return()Sebastian Huber2014-02-211-5/+0
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* bsp/leon3: Add and use LEON3_IrqCtrl_LockSebastian Huber2014-02-192-13/+23
| | | | | Disabling of interrupts is not enough to ensure mutual exclusion on SMP configurations.
* bsp/leon3: Declare LEON3_IrqCtrl_EIrq only onceSebastian Huber2014-02-191-2/+2
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* bsp/leon3: Declare leon3_ext_irq_init() in headerSebastian Huber2014-02-193-4/+5
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* score: Rename rtems_smp_process_interrupt()Sebastian Huber2014-02-195-18/+13
| | | | | | Rename rtems_smp_process_interrupt() into _SMP_Inter_processor_interrupt_handler(). Delete unused header file <rtems/bspsmp.h>.
* score: Rename rtems_smp_secondary_cpu_initialize()Sebastian Huber2014-02-194-4/+8
| | | | | | Rename rtems_smp_secondary_cpu_initialize() into _SMP_Start_multitasking_on_secondary_processor(). Move declaration to <rtems/score/smpimpl.h>.
* score: Delete bsp_smp_broadcast_interrupt()Sebastian Huber2014-02-195-55/+1
| | | | | | Since the per-CPU SMP lock must be acquired and released to send the message a single interrupt broadcast operations offers no benefits. If synchronization is required, then a SMP barrier must be used anyway.
* score: Rename bsp_smp_initialize()Sebastian Huber2014-02-195-5/+5
| | | | | Rename bsp_smp_initialize() into _CPU_SMP_Initialize() since every CPU port must supply this function.
* bsp/leon3: Add and use fatal codesSebastian Huber2014-02-193-3/+7
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* score: Add RTEMS_FATAL_SOURCE_BSPSebastian Huber2014-02-1938-238/+198
| | | | | | Merge RTEMS_FATAL_SOURCE_BSP_GENERIC and RTEMS_FATAL_SOURCE_BSP_SPECIFIC into new fatal source RTEMS_FATAL_SOURCE_BSP. This makes it easier to figure out the code position given a fatal source and code.
* powerpc: Change interrupt disable implemetationSebastian Huber2014-02-1924-71/+10
| | | | | | | | | | | | Instead of SPRG0 (= special purpose register 272) use the new global symbol _PPC_INTERRUPT_DISABLE_MASK to store the interrupt disable mask. The benefit is that it is now possible to disable interrupts without further run-time initialization in boot_card(). At least on Freescale e500 cores this leads also to a faster execution since the mfmsr and mfspr instruction require four cycles to complete. The instructions to load the mask value can execute while the mfmsr is in progress.
* bsp/leon3: Declare amba_initialize()Sebastian Huber2014-02-142-2/+2
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* bsp/leon3: Do not define RTEMS_DEBUGSebastian Huber2014-02-141-11/+12
| | | | | Move vital code out of debug section. Harmonize variable names with other implementations.
* sparc: Add LEON3_ASR17_PROCESSOR_INDEX_SHIFTSebastian Huber2014-02-145-17/+6
| | | | Add _LEON3_Get_current_processor().
* score: Add CPU counter supportSebastian Huber2014-02-1450-5/+243
| | | | | | | | | Add a CPU counter interface to allow access to a free-running counter. It is useful to measure short time intervals. This can be used for example to enable profiling of critical low-level functions. Add two busy wait functions rtems_counter_delay_ticks() and rtems_counter_delay_nanoseconds() implemented via the CPU counter.
* bsps/arm: Fix Cortex-A9 MPCore nanoseconds handlerSebastian Huber2014-02-131-1/+1
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* score: Change debug helper functionsSebastian Huber2014-02-121-1/+1
| | | | | | | | Rename rtems_internal_error_description() to rtems_internal_error_text(). Rename rtems_fatal_source_description() to rtems_fatal_source_text(). Rename rtems_status_code_description() to rtems_status_text(). Remove previous implementation of rtems_status_text().
* sparc: Save/restore only non-volatile contextSebastian Huber2014-02-121-15/+4
| | | | | | | | | | The _CPU_Context_switch() is a normal function call. The following registers are volatile (the caller must assume that the register contents are destroyed by the callee) according to "SYSTEM V APPLICATION BINARY INTERFACE - SPARC Processor Supplement", Third Edition: g1, o0, o1, o2, o3, o4, o5. Drop these registers from the context. Ensure that offset defines match the structure offsets.
* bsps/sparc: Fix ambapp_find_by_idx()Sebastian Huber2014-02-111-1/+1
| | | | The expression "*pi++" post-increments the pointer (not the value).
* bsps/arm: Use Global Timer for Cortex-A9 MPCoreSebastian Huber2014-02-105-29/+78
| | | | | | Use the Global Timer for the Cortex-A9 MPCore clock driver instead of the Private Timer. This enables a consistent nanoseconds since last context switch value across all processors.
* bsps/arm: Include missing header fileSebastian Huber2014-02-103-3/+7
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* Revert "bsp/leon3: New BSP variant leon3_qemu"Sebastian Huber2014-02-079-99/+0
| | | | | | This reverts commit 7579e255127ee0cf04901bbab6c1538559053508. Improve QEMU to support AMBA plug and play instead.
* bsp/leon3: New BSP variant leon3_qemuSebastian Huber2014-02-069-0/+99
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* bsp/leon3: Declare bsp_debug_uart_init() in headerSebastian Huber2014-02-063-5/+5
| | | | Do not return a status.
* score: _CPU_Context_switch_to_first_task_smp()Sebastian Huber2014-02-051-28/+0
| | | | | Delete _CPU_Context_switch_to_first_task_smp() and use _CPU_Context_restore() instead.
* bsps: Delete unused bsp_smp_delay()Sebastian Huber2014-02-052-27/+0
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