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* score: Implement forced thread migrationSebastian Huber2014-05-073-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current implementation of task migration in RTEMS has some implications with respect to the interrupt latency. It is crucial to preserve the system invariant that a task can execute on at most one processor in the system at a time. This is accomplished with a boolean indicator in the task context. The processor architecture specific low-level task context switch code will mark that a task context is no longer executing and waits that the heir context stopped execution before it restores the heir context and resumes execution of the heir task. So there is one point in time in which a processor is without a task. This is essential to avoid cyclic dependencies in case multiple tasks migrate at once. Otherwise some supervising entity is necessary to prevent life-locks. Such a global supervisor would lead to scalability problems so this approach is not used. Currently the thread dispatch is performed with interrupts disabled. So in case the heir task is currently executing on another processor then this prolongs the time of disabled interrupts since one processor has to wait for another processor to make progress. It is difficult to avoid this issue with the interrupt latency since interrupts normally store the context of the interrupted task on its stack. In case a task is marked as not executing we must not use its task stack to store such an interrupt context. We cannot use the heir stack before it stopped execution on another processor. So if we enable interrupts during this transition we have to provide an alternative task independent stack for this time frame. This issue needs further investigation.
* bsps/arm: Declare return typesSebastian Huber2014-05-071-7/+8
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* bsps: Fix BSP_INITIAL_EXTENSIONSebastian Huber2014-05-071-1/+1
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* multiple BSPs: Remove BSP_SMALL_MEMORYJoel Sherrill2014-05-0614-35/+0
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* bsp/gen83xx: Add BSP_USB_EHCI_MPC83XX_HAS_ULPISebastian Huber2014-05-061-0/+3
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* testsuite: Add a per BSP test check for tests not to build.Chris Johns2014-05-0530-0/+416
| | | | | | | | Provide a file per BSP to list tests that do not build for a BSP. This change removes the BSP_SMALL_MEMORY hack from the code. That hack was a mistake. Provide configuration files for each BSP with tests that cannot build.
* libchip: Add asserts to dwmac driverRalf Kirchner2014-04-301-0/+3
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* libchip: Correct netstats message for dwmac driverRalf Kirchner2014-04-301-1/+1
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* bsp/altera-cyclone-v: Move mbufs and network clusters to uncached RAMRalf Kirchner2014-04-301-0/+12
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* bsp/altera-cyclone-v: Increase size of nocache region and nocache heapRalf Kirchner2014-04-302-3/+3
| | | | Increase size of nocache heap in order to be able to move mbufs and clusters of the network driver to uncached RAM
* score: Statically initialize _ISR_Vector_tableSebastian Huber2014-04-293-3/+1
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* bsps/mips: Delete unused filesSebastian Huber2014-04-2915-705/+0
| | | | The MIPS port defines CPU_SIMPLE_VECTORED_INTERRUPTS to FALSE.
* bsps/m32r: Fix bsp_specsSebastian Huber2014-04-291-6/+4
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* bsps/bfin: Fix bsp_specsSebastian Huber2014-04-295-25/+12
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* bsp/h8sim: Fix linker command fileSebastian Huber2014-04-291-0/+2
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* sparc: Add _CPU_Get_current_per_CPU_control()Sebastian Huber2014-04-282-60/+33
| | | | | | | | | | | | | | | | Use register g6 for the per-CPU control of the current processor. The register g6 is reserved for the operating system by the SPARC ABI. On Linux register g6 is used for a similar purpose with the same method since 1996. The register g6 must be initialized during system startup and then must remain unchanged. Since the per-CPU control is used in all critical sections of the operating system, this is a performance optimization for the operating system core procedures. An additional benefit is that the low-level context switch and interrupt processing code is now identical on non-SMP and SMP configurations.
* sparc: Optimize context switchSebastian Huber2014-04-281-4/+2
| | | | | | The registers g2 through g4 are reserved for applications. GCC uses them as volatile registers by default. So they are treated like volatile registers in RTEMS as well.
* mcf52235/configure.ac: Delete junk lineJoel Sherrill2014-04-241-1/+0
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* bootstrap: Sort the contents of the prinstall.am files.Chris Johns2014-04-232-4/+4
| | | | | Sorting removed the variations across different host operating systems and file systems.
* shsim: Correct linking for C++Joel Sherrill2014-04-222-16/+13
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* gensh4: Correct linking for C++Joel Sherrill2014-04-222-42/+8
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* gensh2: Correct linking for C++Joel Sherrill2014-04-222-16/+8
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* gensh1: Correct linking for C++Joel Sherrill2014-04-222-16/+8
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* score603e: Add rtems_crtiJoel Sherrill2014-04-221-3/+3
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* ss555: Add rtems_crti/nJoel Sherrill2014-04-223-3/+17
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* sim68000/bsp_specs: Add crtbegin/end, crt[in]Joel Sherrill2014-04-221-2/+5
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* mpc8260ads: Add rtems_crti/nJoel Sherrill2014-04-223-6/+13
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* h8sim/bsp_specs: Add crtbegin/end, crt[in]Joel Sherrill2014-04-221-1/+4
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* niagara/Makefile.am: Fix rule for start.oJoel Sherrill2014-04-221-1/+1
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* libcpu/sh: Build cache stubs so apps usign cache API linkJoel Sherrill2014-04-226-11/+46
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* dummy_printk_support.c: Comment clean upJoel Sherrill2014-04-221-6/+9
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* shsim: Add printk() support and move all code to console subdirectoryJoel Sherrill2014-04-224-10/+55
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* bsps: Fix TLS support in linker command filesSebastian Huber2014-04-2278-78/+234
| | | | | The TLS section symbols had wrong values in case of an empty TLS data section and a nonempty TLS BSS section.
* bsp/mbx8xx: Fix Makefile.am and bsp_specsSebastian Huber2014-04-224-7/+27
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* bsps/powerpc: Fix linker command filesSebastian Huber2014-04-223-11/+7
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* bsp/arm: Cleanup L2 cache handlingRalf Kirchner2014-04-171-38/+7
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* bsp/arm: Correct L2 cache enable methodRalf Kirchner2014-04-171-53/+48
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* bsp/arm: Add cache size methodsRalf Kirchner2014-04-172-0/+115
| | | | Add new methods which deliver the cache sizes of for supported cache levels.
* bsp/arm: Add L2 cache lockingRalf Kirchner2014-04-171-9/+34
| | | | This level 2 cache is a shared data and instruction cache and thus needs locking.
* bsp/arm: Remove unused cache store methodsRalf Kirchner2014-04-172-30/+0
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* bsp/arm: Correct cache misalignment handlingRalf Kirchner2014-04-172-32/+60
| | | | Correct misalignment handling and prepare for locking.
* bsp/arm: Correct L2 cache flushingRalf Kirchner2014-04-171-17/+31
| | | | Correct misalignment handling and prepare for locking.
* bsp/arm: Remove arm erratum 764369 from L2 cacheRalf Kirchner2014-04-171-14/+0
| | | | Arm erratum 764369 only applies to the level 1 cache.
* bsp/arm: Consistenly same handling for flushingRalf Kirchner2014-04-171-2/+2
| | | | | It is importeant to consistently apply the same handling for flushing within level 2 and level 1 cache handling. In this case now both handling use clean and invalidate.
* bsp/arm: RTEMS_SMP to arm erratum 764369 detectionRalf Kirchner2014-04-173-10/+8
| | | | Move the RTEMS_SMP conditional compilation to the detection method of arm erratum 764369
* bsp/arm: Erratum 764369 after enabling SCURalf Kirchner2014-04-171-1/+1
| | | | Execute the SCU part of the workaround of arm erratum 764368 after the SCU was enabled.
* bsp/arm: Correct detection of arm erratum 764368Ralf Kirchner2014-04-171-0/+1
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* bsp/arm: Cleanup L1 cacheRalf Kirchner2014-04-171-2/+2
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* libchip: Correct error handling in dwmac driverRalf Kirchner2014-04-171-11/+4
| | | | By fault an rtems_status_code has been expected instead of an errno error number.
* libchip: Reduce tx interruptsRalf Kirchner2014-04-174-222/+262
| | | | | | | Reduce number of packet transmitted interrupts by using the interrupt mechanism only if we run out of DMA descriptors. Under normal conditions regaining DMA descriptors, mbufs and clusters is handled via a counter.
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