| Commit message (Collapse) | Author | Age | Files | Lines |
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This patch adapts the previously added Beaglebone PWM code from BBBIO to RTEMS.
This work was done in the context of the Google Summer of Code 2016, and further
patches will follow to improve the code quality and documentation.
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This patch adds the PWM driver code for the Beaglebone Black from BBBIO:
https://github.com/VegetableAvenger/BBBIOlib/blob/master/BBBio_lib/BBBiolib_PWMSS.c
This commit is for tracking purposes only; the next commit will adapt the code for
RTEMS.
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The basic data and instruction rage functions should be compatible
for all ARMv4,5,6,7 functions. On the other hand, some functions
are not portable, for example arm_cp15_data_cache_test_and_clean()
and arm_cp15_data_cache_invalidate() for all versions and there
has to be specialized version for newer cores.
arm_cache_l1_properties_for_level uses CCSIDR which is not present
on older chips.
Actual version is only experimental, needs more changes
and problem has been found on RPi1 with dlopen so there seems
to be real problem.
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BSPs.
The original ARM architecture wide cache_.h is changed to dummy version
for targets not implementing/enablig cache at all.
The ARM targets equipped by cache should include
appropriate implementation.
Next options are available for now
c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h
basic ARM cache integrated on the CPU core directly
which requires only CP15 oparations
c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
support for case where ARM L2C-310 cache controller
is used. It is accessible as mmaped peripheral.
c/src/lib/libbsp/arm/shared/armv7m/include/cache_.h
Cortex-M specific cache support
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and maximal alignment.
There is need for unambiguous named and defined cache function
which should be called when code is updated, loaded
or is self-modifying.
There should be function to obtain maximal cache line length
as well. This function can and should be used for allocations
which can be used for data and or code and ensures that
there are no partial cache lines overlaps on start and
end of allocated region.
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The arm_cp15_data_cache_clean_and_invalidate leads to hang on RPi2,
clean by individual lines works on RPi1 and RPi2.
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This support is required when newer firmware is used on
Raspberry Pi 2 boards.
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When HYP mode is detected at startup then setup HYP mode
vectors table (for future extensions) clean exceptions
switching to HYP mode and switch CPU to ARM SVC mode.
BSPs which want to use this support need to include next option
in their configure.ac
RTEMS_BSPOPTS_SET([BSP_START_IN_HYP_SUPPORT],[*],[1])
RTEMS_BSPOPTS_HELP([BSP_START_IN_HYP_SUPPORT], [Support start of BSP in ARM HYP mode])
AM_CONDITIONAL(BSP_START_IN_HYP_SUPPORT,test "$BSP_START_IN_HYP_SUPPORT" = "1")
and need to include next lines in corresponding Makefile.am
if BSP_START_IN_HYP_SUPPORT
libbsp_a_SOURCES += ../shared/startup/bsp-start-in-hyp-support.S
endif
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base access.
The main reason for inclusion of minimum hypervisor related defines
is that current ARM boards firmware and loaders (U-boot for example)
start loaded operating system kernel in HYP mode to allow it take
control of virtualization (Linux/KVM for example).
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We may have more than one idle thread. Thus, the clock driver fast idle
logic would be a bit more complicated.
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According to the C11 standard only atomic read-modify-write operations
guarantee that the last value written in modification order is read, see
"7.17.3 Order and consistency". Thus we must use a read-modify-write in
_SMP_Inter_processor_interrupt_handler() to make sure we read an
up-to-date message.
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Some changes have been reverted to keep readability.
For example squash of BCM2835_MBOX_TAG_* defines
which are visually aligned in column.
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Added functions for retrieving firmware revision,
board model and board revision.
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Import the <arpa/inet.h> from current FreeBSD. Necessary due to changes
in <netinet/in.h>. Remove BSD hack from <arpa/inet.h>.
Clean up problems with htonl(). These functions are defined in
<arpa/inet.h>. This lead to some problems because they are defined in
<rtems/endian.h> too. Add NTOHL, ... to
<rtems/rtems_bsdnet_internal.h>.
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This solution is quick fix until CPU_DATA_CACHE_ALIGNMENT is defined
and cache manager is checked on all Raspberry Pi variants.
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We support read/write of arbitrary buffers.
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The RTEMS print user need to know nothing about a particular printer
implementation. In particular get rid of the <stdio.h> include which
would be visible via <rtems.h>.
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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clear of alt outputs.
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TMS570LS3135ZWT chip.
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Close #2684.
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Rework CPU counter support to enable use of the GR740 up-counter via
%asr22 and %asr23.
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synchronized through cache.
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Close #2742.
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Add CLOCK_DRIVER_USE_ONLY_BOOT_PROCESSOR clock driver option. If
defined, then do the clock tick processing on the boot processor on
behalf of all other processors. Currently, this is intended as a
workaround for a Qemu shortcoming on ARM.
Update #2737.
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Some boards require this size.
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Do not wait for the interrupt server while owning the allocator lock.
This could lead to deadlock in case one of interrupt service routines or
user extensions want to obtain the allocator mutex as well. Instead let
the interrupt server do the install/remove job entirely on behalf of the
requesting task.
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