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* rtems_cache_invalidate_multiple_instruction_linesAleksandr Platonov2014-01-141-1/+1
| | | | | | | | According with comment in rtems_cache_invalidate_multiple_instruction_lines(), final_address indicates the last address which needs to be invalidated. But if in while loop we got final_address == i_addr condition then loop breaks and final_address will not be invalidated.
* SPI SD-Card: setup valid CRC-7 for STOP_TRANSMISSION command.Pavel Pisa2013-10-081-0/+5
| | | | | | | | | | | | STOP_TRANSMISSION command is used to finish READ_MULTIPLE_BLOCK command and its format is regular command format. It requires valid CRC-7 to have effect at least on same cards types else it is ignored and attempt to issue next READ or WRITE commands results in illegal command condition (0x04) preceded by strange (0x3f) for tested card. Signed-off-by: Pavel Pisa <ppisa@pikron.com>
* Backport of development SPI SD-card patches to RTEMS 4.10.Pavel Pisa2013-10-082-47/+176
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Arnout Vandecappelle: PR 1569/misc * libchip/i2c/spi-sd-card.c: Added CRC checks. PR 1576/misc * libchip/i2c/spi-sd-card.c: Enable CRC checks. PR 1567/misc * libchip/i2c/spi-sd-card.h, libchip/i2c/spi-sd-card.c: Fixed timeouts. PR 1579/misc * libchip/i2c/spi-sd-card.c: Gradually increasing sleep times when waiting for write to finish. PR 1580/misc * libchip/i2c/spi-sd-card.c: Use bigger chunks and yield processor while waiting for read data. PR 1586/misc * libchip/i2c/spi-sd-card.h, libchip/i2c/spi-sd-card.c: Add retries to SD card accesses. Signed-off-by: Pavel Pisa <ppisa@pikron.com>
* bsp/csb336: Memory map update to support i.MX1 based PiMX1 as well.Pavel Pisa2013-08-191-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CSB336 i.MX1/i.MXS memory map organization - SDRAM starts at address 0x08000000 but 2 MB are reserved for boot-block/loader (or other use) before RTEMS image origin/load address (that is kept from previous setup) - Caching of 30 MB of SDRAM used for RTEMS (start at 0x08200000) is changed to writeback mode which provides higher throughput. - The first 1 MB of RTEMS dedicated SDRAM is remapped to address 0 to provide area for ARM CPU exceptions table. - Internal registers and rest of the Flash (above 1 MB) are mapped one to one. Registers region is extended to 2 MB to cover eSRAM found on i.MX1 chip variant. - The first two megabytes of SDRAM unused by RTEMS are mapped with attributes to allow specific purposes. - the first MB (at address 0x08000000) is nocached to allow directly set some values read by booot-block after warm reset - the second MB (at address 0x08100000) is set for write-through caching. That allows to use memory for LCD frame-buffer without need to flush cache after each redraw. Signed-off-by: Pavel Pisa <pi@baree.pikron.com>
* bsp/csb336: implement bsp_interrupt_vector_enable/disable.Pavel Pisa2013-08-191-0/+10
| | | | Signed-off-by: Pavel Pisa <ppisa@pikron.com>
* bsp/csb336: mc9328mxl correct AITC access in bsp_interrupt_dispatch.Pavel Pisa2013-08-191-1/+2
| | | | | | | | | | | The original version is missing void and result is that (*x >> 16) is optimized to ldh rX,[rY]. But it is not allowed/supported to access bus/address range used by AITC by other than 32 bit wide accesses and 16-bit access results in the data abort exception. The corrected version works on real hardware and is even more readable. Signed-off-by: Pavel Pisa <ppisa@pikron.com>
* Add c++ guard to header.Daron Chabot2013-05-161-0/+8
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* Remove stray '/'.Ralf Corsépius2012-10-101-1/+1
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* Delete lingering bspopts.h.in fileGedare Bloom2012-08-091-88/+0
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* Use http://www.rtems.org/bugzilla as bug-URL.Ralf Corsépius2012-08-0913-13/+13
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* bsp/genmcf548x: Enable FPU in BSP startup codeSebastian Huber2012-05-021-13/+5
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* bsp/genmcf548x: Fix BSP optionsSebastian Huber2012-05-021-3/+4
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* PR 2015 - LEON3: make SHM driver configurable using weak symbolsJoel Sherrill2012-02-172-5/+22
| | | | | | | | | | | PR 2015/bsps Since the configuration struct is always present one can let DATA initialize it to reduce footprint, at the same time it is made weak to let the user able to configure the SHM driver without editing the driver code. Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
* PR 1962/bsps - MVME162 Console Corrections and ImprovementsJoel Sherrill2012-02-027-23/+336
| | | | | | | | | | | | | | | | | | * console/console.c: char_ready() was never returning true so console never processed input data * console/console.c: added printk() support to default device * include/bsp.h: Added #define for MOT_162BUG_VEC_ADDRESS * startup/bspclean.c: Modified to use MOT_162BUG_VEC_ADDRESS * startup/bspstart.c: Modified to use MOT_162BUG_VEC_ADDRESS * make/custom/mvme162.cfg: Modified to use "RTEMS_CPU_MODEL=68lc040" and "CPU_CFLAGS = -mcpu=68040 -msoft-float" so BSP will always work with all board variations. * README: Added notes on user required configuration changes and information about board models and variants * README.models: New file that contains a detailed list of MVME162 models and variants. Signed-off-by: Vic Hoover <victor.hoover.ctr@navy.mil>
* PR 2011/networking - GRETH: performance improvements and one bugfixJoel Sherrill2012-02-021-179/+316
| | | | | | | | | | | | GRETH driver updated, 10-15% performance improvements for GBIT MAC, unnecessary RX interrupts not taken which under heavy load saves approx. 1500 interrupts/s, one task removed saving about 5kb memory and 1 bug solved. BUG: RX interrupt was enabled before the RX-daemon was created which could result in a faulty call to rtems_event_send. Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
* PR 2011/networking GRETH: Moved print to remove potential deadlockJoel Sherrill2012-02-021-2/+11
| | | | | | | | | Deadlock may arise when the EDCL bug link is used to tunnel console output over Ethernet, when Ethernet is down one should avoid using console (only during debugging of LEON targets) Author: Marko Isomaki <marko@gaisler.com> Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
* LEON3: change d-cache snoop detect implementationDaniel Hellstrom2012-02-021-7/+5
| | | | | | | | | | PR 2010/bsps The previous code only checked if d-cache snooping was implemented, however snooping may be available but not enabled which may lead to driver bugs. Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
* LEON3: CPU index intialization moved to bspstart.cJoel Sherrill2012-02-022-18/+18
| | | | | | | | | | | | | | | | | 2009/bsps All LEON3/4 systems have a CPU-id, if on a single-CPU system the ID is always zero. On a multicore system it ranges from 0 to 15. The CPU index should always by updated even in a non-MP RTEMS OS since the CPU running RTEMS may not always be CPU0. For example when RTEMS runs on CPU1 and Linux on CPU0 in a mixed ASMP system. The old code executed within the IRQ controller initialization code makes no sense since the ASR register is a CPU register, it has nothing to do with AMBA initialization either. Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
* LEON3: fix compiler warning in SHM driverDaniel Hellstrom2012-02-021-1/+1
| | | | | | PR 2008/bsps Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
* Add .git ignore. Remove .cvsignoreJoel Sherrill2012-02-021-0/+1
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* Add .git ignore. Remove .cvsignoreJoel Sherrill2012-02-02322-1636/+0
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* LEON3BSP MP: may wake one more CPU than expectedDaniel Hellstrom2012-02-021-1/+1
| | | | | | | | | | The SHM code always wakes one CPU more that configured, however this has never been a problem since RTEMS will be running on all CPUs or only two cores were available. PR 2006/bsps Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
* Upgrade to 4.10.24.10.2Joel Sherrill2011-12-131-1/+1
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* 2011-11-09 Jennifer Averett <jennifer.averett@oarcorp.com>Joel Sherrill2011-11-092-1/+6
| | | | | PR 1934/bsps * libchip/serial/ns16550.c: Change to unsigned variable.
* 2011-08-15 Julien Delange <julien.delange@gmail.com>Sebastian Huber2011-08-154-3/+11
| | | | | | | * irq/irq.c: Removed printk() before the interrupt initialization because it somehow destroys the interrupt context. * make/custom/nds.cfg: Enable Thumb interwork. * startup/bspstart.c: Set default exception handler.
* 2011-07-22 Joel Sherrill <joel.sherrilL@OARcorp.com>Joel Sherrill2011-07-222-4/+7
| | | | | | PR 1845/bsps * make/custom/rtl22xx_t.cfg: Remove unused line with what is now invalid syntax.
* 2011-07-21 Jorge Lopez <jorge.lopez.trescastro@esa.int>Joel Sherrill2011-07-212-0/+7
| | | | | PR 1766/bsps * clock/ckinit.c: Add missing read of Timer_Counter_1.
* Upgrade to 4.10.14.10.1Joel Sherrill2011-07-211-1/+1
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* 2011-07-20 Till Straumann <strauman@slac.stanford.edu>Joel Sherrill2011-07-203-22/+33
| | | | | | PR 1837/bsps * shared/motorola/motorola.c, shared/motorola/motorola.h: Add MVME2400 board with 750 CPU to list of supported Motorola boards.
* formatting.Joel Sherrill2011-07-201-1/+1
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* 2011-07-14 Joel Sherrill <joel.sherrilL@OARcorp.com>Joel Sherrill2011-07-143-0/+17
| | | | * .cvsignore, include/.cvsignore: New files.
* 2011-07-14 Till Straumann <strauman@slac.stanford.edu>Joel Sherrill2011-07-142-8/+12
| | | | | | PR 1833/bsps * ne2000/ne2000.c: Addition of multicast support disabled broadcast reception. Patch also includes support to work on big endian CPUs.
* 2011-07-13 Sebastian Huber <sebastian.huber@embedded-brains.de>Joel Sherrill2011-07-132-1/+17
| | | | | | | | | | PR 1832/libcpu * at91rm9200/irq/irq.c: he bsp_interrupt_dispatch routine does not determine the correct interrupt source number. According to the datasheet, the reading of the interrupt vector register (AIC_IVR) notifies the hardware that the OS is taken care of the interrupt. Only after AIC_IVR have been read can the correct source number be read from the interrupt status register (AIC_ISR).
* 2011-04-10 Kate Feng <feng@bnl.gov>Joel Sherrill2011-06-1714-81/+123
| | | | | | | | | | | | | PR 1786/bsps * Makefile.am: Add support for Altivec. * startup/bspstart.c, Makefile.am: Use shared/startup/zerobss.c instead. * make/custom/mvme5500.cfg: Change CPU_CFLAGS to "-mcpu=7450 -mtune=7450 -Dmpc7455" * irq/BSP_irq.c, pci/detect_host_bridge.c, pci.c, pcifinddevice.c: Remove warnings. * vme/VMEConfig.h, include/bsp.h: use VME shared IRQ handlers. * network/if_100MHz/GT64260eth.c: Recycle the Rx mbuf if there is any Rx error.
* Fix formatting.Joel Sherrill2011-06-171-15/+18
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* Merge with CVS-HEAD.Ralf Corsepius2011-05-254-21/+26
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* 2011-05-18 Till Straumann <strauman@slac.stanford.edu>Till Straumann2011-05-182-1/+7
| | | | | | PR1797/bsps * shared/bootcard.c: Fixed a typo (in code, not comment) which I introduced with the last change.
* 2011-05-18 Till Straumann <strauman@slac.stanford.edu>Till Straumann2011-05-1825-43/+231
| | | | | | PR1797/bsps: Applied cleaned-up version of Kate's patch. CONFIGURE_MALLOC_BSP_SUPPORTS_SBRK is now a 'bspopts.h' setting and as such configurable.
* 2011-05-16 Till Straumann <strauman@slac.stanford.edu>Till Straumann2011-05-162-0/+6
| | | | * include/bsp.h: define CONFIGURE_MALLOC_BSP_SUPPORTS_SBRK
* 2011-05-06 Sebastian Huber <sebastian.huber@embedded-brains.de>Sebastian Huber2011-05-063-5/+12
| | | | | | * include/bsp.h: Moved NEED_LOW_LEVEL_INIT define because it has to be visible for the assembler. * startup/linkcmds.brs5l: Fixed RAM size.
* 2011-04-25 Jennifer Averett <jennifer.averett@OARcorp.com>Joel Sherrill2011-04-256-24/+18
| | | | | | PR 1783/bsps * include/bsp.h: Remove dead prototypes of Clock_delay() and delay(). Neither had bodies.
* 2011-04-22 Joel Sherrill <joel.sherrilL@OARcorp.com>Joel Sherrill2011-04-222-1/+4
| | | | * console/console.c: Now compiles.
* 2011-04-20 Joel Sherrill <joel.sherrilL@OARcorp.com>Joel Sherrill2011-04-202-0/+6
| | | | * acinclude.m4: Regenerated for TLL6527M.
* Fix formatting.Joel Sherrill2011-04-203-29/+8
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* 2011-04-20 Rohan Kangralkar <rkangral@ece.neu.edu>Joel Sherrill2011-04-204-17/+47
| | | | | | | PR 1781/bsps * console/console-io.c: The UART RX and TX are different ISR now. So the array containing the registeration changes. The change is due to change in the libcup uart function.
* 2011-04-20 Rohan Kangralkar <rkangral@ece.neu.edu>Joel Sherrill2011-04-2014-0/+1178
| | | | | | | | | | | PR 1781/bsps * ChangeLog, Makefile.am, README, bsp_specs, configure.ac, preinstall.am, times, console/console.c, include/bsp.h, include/cplb.h, include/tm27.h, make/custom/TLL6527M.cfg, startup/bspstart.c, startup/linkcmds: New files. Initial port for the TLL6527Mboard that contains blackfin 52X range of processors. Used eZKit533 as a reference for building the port.
* 2011-04-20 Rohan Kangralkar <rkangral@ece.neu.edu>Joel Sherrill2011-04-2010-164/+1481
| | | | | | | | | | | | | | PR 1781/bsps * bf52x/include: Added additional MMR. * bf52x/interrupt: The BF52X processors have a different System interrupt controller than present in the 53X range of processors. The 52X have 8 interrupt assignment registers. The implementation uses tables to increase predictability. * serial/uart.?: Added DMA based and interrupt based transfer support. The uart code used a single ISR for TX and RX and tried to identify and multiplex inside the ISR. In the new code the type of interrupt is identified by the central ISR dispatcher bf52x/interrupt or interrupt/. This simplifies the UART ISR.
* 2011-04-11 Keith Robertson <kjrobert at alumni dot uwaterloo dot ca>Joel Sherrill2011-04-112-3/+45
| | | | | * ne2000/ne2000.c: Add multicast support. Patch submitted to mailing list 2005-12-21.
* 2011-04-04 Joel Sherrill <joel.sherrilL@OARcorp.com>Joel Sherrill2011-04-042-0/+15
| | | | | | | | PR 1768/bsps * shared/irq/irq_asm.S: The nbench benchmark highlighted the fact that we do not perform a cld before calling C code in the ISR. This was historically not a problem but gcc 4.3 changed the behavior. From http://gcc.gnu.org/gcc-4.3/changes.html
* 2011-03-22 Joel Sherrill <joel.sherrilL@OARcorp.com>Joel Sherrill2011-03-222-6/+11
| | | | | PR 1772/bsps * console/sci.c: Use same default baud rate as monitor.
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