summaryrefslogtreecommitdiffstats
path: root/c/src (follow)
Commit message (Collapse)AuthorAgeFilesLines
* sparc64: fix copyright notices.Gedare Bloom2015-02-238-34/+14
| | | | | The sparc64 port had some incorrect copyright notices affixed to source code files.
* ARM: Support VFP-D16Martin Galvan2015-02-201-3/+5
| | | | | | | | | This patch allows the existing FPU code to support both VFP-D16 and VFP-D32. According to ARM, writes to D32DIS are ignored for D16 so there's no need to enclose the bic instruction with an #ifdef. We tested it on a TMS570LS3137 using TI initialization code and it works fine. Signed-off by: Martin Galvan <martin.galvan@tallertechnologies.com>
* score: Add _CPU_SMP_Prepare_start_multitasking()Sebastian Huber2015-02-174-8/+19
| | | | Update #2268.
* lpc1768_mbed_ahb_ram_eth-testsuite.tcfg: Add ftp01Joel Sherrill2015-02-131-0/+1
|
* lpc1768_mbed-testsuite.tcfg: Add ftp01Joel Sherrill2015-02-131-0/+1
|
* IMFS: Add fine grained configurationSebastian Huber2015-02-121-1/+0
| | | | | | | | | | | | | | | | | | Remove miniIMFS. Statically initialize the root IMFS. Add configuration options to disable individual features of the root IMFS, e.g. o CONFIGURE_IMFS_DISABLE_CHOWN, o CONFIGURE_IMFS_DISABLE_FCHMOD, o CONFIGURE_IMFS_DISABLE_LINK, o CONFIGURE_IMFS_DISABLE_MKNOD, o CONFIGURE_IMFS_DISABLE_MOUNT, o CONFIGURE_IMFS_DISABLE_READLINK, o CONFIGURE_IMFS_DISABLE_RENAME, o CONFIGURE_IMFS_DISABLE_RMNOD, o CONFIGURE_IMFS_DISABLE_SYMLINK, o CONFIGURE_IMFS_DISABLE_UNMOUNT, and o CONFIGURE_IMFS_DISABLE_UTIME.
* grspw: Fix typosDaniel Cederman2015-02-111-3/+3
|
* bsp/sparc: Move BSP_ISR_handler to a separate file and rename itDaniel Cederman2015-02-119-23/+59
| | | | | | | This allows it to be wrapped by another function at link-time and can be used to trace interrupts. If not placed in a separate file, the function pointer address used in BSP_shared_interrupt_init will be resolved at compile-time, and the function will not be wrappable.
* Filesystem: Delete unused fsmountme_h handlerSebastian Huber2015-02-091-1/+0
|
* arm/tms570: sci context has to be writable because it holds state variable.Pavel Pisa2015-02-042-4/+4
| | | | | | | | | | | | | | The structure tms570_sci_context holds state variable tx_chars_in_hw which holds if and how many characters (in the optional FIFO support for some Ti SCIs) are submitted into hardware. When field is not writable then code breaks when RTEMS is build for Flash area. The problem found and analyzed by Martin Galvan from tallertechnologies. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* bsps/powerpc: Fix a clock driverNick Withers2015-01-301-9/+57
| | | | | | | PowerPC Book E: Account for an extra tick period if a tick increment's pending. Close #2230.
* mcf5206elite/include/i2c.h: Fix spelling errorJoel Sherrill2015-01-231-1/+1
|
* stm32f4/.../stm32f105rc-testsuite.tcfg: Add more testsJoel Sherrill2015-01-231-0/+1
|
* lpc24xx/.../lpc23xx_tli800-testsuite.tcfg: Add more testsJoel Sherrill2015-01-231-0/+7
|
* lpc24xx/.../lpc2362-testsuite.tcfg: Add more testsJoel Sherrill2015-01-231-0/+2
|
* lm3s69xx/.../lm3s6965-testsuite.tcfg: Add more testsJoel Sherrill2015-01-231-0/+1
|
* lm3s69xx/.../lm3s3749-testsuite.tcfg: Add more testsJoel Sherrill2015-01-231-0/+2
|
* bsp/altera-cyclone-v: Use proper free functionSebastian Huber2015-01-231-1/+1
|
* bsps/sparc: Use calloc()Sebastian Huber2015-01-231-3/+1
| | | | Close #2242.
* bsps/powerpc: Fix switch statement in CPU identSebastian Huber2015-01-231-0/+2
| | | | Close #2237.
* libchip: Fix high capacity detection for MMCSebastian Huber2015-01-231-1/+1
| | | | Close #2239.
* grspw: descriptor tables no longer statically allocatedjavamonn2015-01-221-7/+7
|
* Filesystem: Delete node type operationSebastian Huber2015-01-221-7/+8
| | | | Use the fstat handler instead.
* powerpc: Fix AltiVec VSCR save/restoreSebastian Huber2015-01-201-4/+6
|
* bsps/powerpc: Fix conditional compilationSebastian Huber2015-01-141-3/+1
|
* bsp/mcf5206elite: Remove <i2c.h> inlude in <bsp.h>Sebastian Huber2015-01-142-3/+1
| | | | This prevents a compile-time error in libtests/i2c01.
* libcpu/powerpc/mpc6xx/mmu/bat.c: Now compiles with gcc 5.xJoel Sherrill2015-01-131-12/+12
|
* bsp/qoriq: Add T2080RDB and T4240RDB variantsSebastian Huber2015-01-1324-318/+714
|
* powerpc: AltiVec and FPU context supportSebastian Huber2015-01-137-12/+821
| | | | | | | | | | | Add AltiVec and FPU support to the Context_Control in case we use the e6500 multilib. Add PPC_MULTILIB_ALTIVEC and PPC_MULTILIB_FPU multilib defines. Add non-volatile AltiVec and FPU context to Context_Control. Add save/restore of non-volatile AltiVec and FPU to _CPU_Context_switch(). Add save/restore of volatile AltiVec and FPU context to the exception code. Adjust data cache optimizations for the new context and cache line size.
* bsps/powerpc: Use e500 exc categories for e6500Sebastian Huber2015-01-131-0/+1
| | | | This is not correct, but works for now.
* moxiesim: Add conditional logic to handle old and new gas syntaxAnthony Green2015-01-102-2/+21
|
* powerpc: Use PPC_HAS_FPUSebastian Huber2015-01-091-6/+6
| | | | Provide floating point context support only if PPC_HAS_FPU == 1.
* powerpc: Set PPC_DEFAULT_CACHE_LINE_SIZE for e6500Sebastian Huber2015-01-091-15/+11
|
* powerpc: Use PPC_DEFAULT_CACHE_LINE_SIZESebastian Huber2015-01-091-8/+2
| | | | | Use it for the default PPC_CACHE_ALIGNMENT. Use it for PPC_STRUCTURE_ALIGNMENT.
* powerpc: Use alternate time base for CPU counterSebastian Huber2015-01-091-1/+1
|
* bsp/qoriq: Fix nanoseconds extensionSebastian Huber2015-01-091-4/+17
|
* bsp/qoriq: Increase MAS0[ESEL] widthSebastian Huber2015-01-091-3/+3
|
* bsp/qoriq: Add MAS7 support for MMUSebastian Huber2015-01-097-21/+50
| | | | | This enables usage of the full real address space which is 40-bit on the T2080 for example.
* bsps/powerpc: ppc_exc_initialize_interrupt_stack()Sebastian Huber2015-01-092-11/+20
|
* bsps/powerpc: Add TMR access macrosSebastian Huber2015-01-091-0/+28
|
* bsps/powerpc: Add cache size functionsSebastian Huber2015-01-091-0/+46
|
* bsps/powerpc: Delete C pre-processor warningSebastian Huber2015-01-091-2/+0
| | | | Do not warn about not implemented cache functions.
* bsps/powerpc: Support for 64 byte cache linesSebastian Huber2015-01-091-6/+23
|
* bsps/powerpc: Support a cache alignment of 64Sebastian Huber2015-01-091-1/+8
| | | | Give the BSP the ability to define PPC_CACHE_ALIGNMENT.
* bsps/powerpc: Support e6500 indentificationSebastian Huber2015-01-092-0/+12
|
* bsps/u-boot: Add optional text and data sectionsSebastian Huber2015-01-091-4/+12
|
* bsps/u-boot: Update due to API changesSebastian Huber2015-01-093-7/+155
|
* bsps/mpc83xx: Fix warningsSebastian Huber2015-01-091-4/+5
|
* smp: Add and use _SMP_Should_start_processor()Sebastian Huber2015-01-092-10/+2
|
* pc386: Add Edison base supportJoel Sherrill2015-01-0412-17/+220
| | | | | | | | | The current support for the Edison supports a single polled UART for input and output plus a simulated clock tick. The activities forward for supporting the Edison have been posted on the RTEMS mailing lists and at: http://rtemsramblings.blogspot.com/2014/12/intel-edison-and-rtems-road-forward.html
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-28 10:39:06 +0000