summaryrefslogtreecommitdiffstats
path: root/c/src (follow)
Commit message (Collapse)AuthorAgeFilesLines
* ss555: Add rtems_crti/nJoel Sherrill2014-04-223-3/+17
|
* sim68000/bsp_specs: Add crtbegin/end, crt[in]Joel Sherrill2014-04-221-2/+5
|
* mpc8260ads: Add rtems_crti/nJoel Sherrill2014-04-223-6/+13
|
* h8sim/bsp_specs: Add crtbegin/end, crt[in]Joel Sherrill2014-04-221-1/+4
|
* niagara/Makefile.am: Fix rule for start.oJoel Sherrill2014-04-221-1/+1
|
* libcpu/sh: Build cache stubs so apps usign cache API linkJoel Sherrill2014-04-226-11/+46
|
* dummy_printk_support.c: Comment clean upJoel Sherrill2014-04-221-6/+9
|
* shsim: Add printk() support and move all code to console subdirectoryJoel Sherrill2014-04-224-10/+55
|
* bsps: Fix TLS support in linker command filesSebastian Huber2014-04-2278-78/+234
| | | | | The TLS section symbols had wrong values in case of an empty TLS data section and a nonempty TLS BSS section.
* bsp/mbx8xx: Fix Makefile.am and bsp_specsSebastian Huber2014-04-224-7/+27
|
* bsps/powerpc: Fix linker command filesSebastian Huber2014-04-223-11/+7
|
* bsp/arm: Cleanup L2 cache handlingRalf Kirchner2014-04-171-38/+7
|
* bsp/arm: Correct L2 cache enable methodRalf Kirchner2014-04-171-53/+48
|
* bsp/arm: Add cache size methodsRalf Kirchner2014-04-172-0/+115
| | | | Add new methods which deliver the cache sizes of for supported cache levels.
* bsp/arm: Add L2 cache lockingRalf Kirchner2014-04-171-9/+34
| | | | This level 2 cache is a shared data and instruction cache and thus needs locking.
* bsp/arm: Remove unused cache store methodsRalf Kirchner2014-04-172-30/+0
|
* bsp/arm: Correct cache misalignment handlingRalf Kirchner2014-04-172-32/+60
| | | | Correct misalignment handling and prepare for locking.
* bsp/arm: Correct L2 cache flushingRalf Kirchner2014-04-171-17/+31
| | | | Correct misalignment handling and prepare for locking.
* bsp/arm: Remove arm erratum 764369 from L2 cacheRalf Kirchner2014-04-171-14/+0
| | | | Arm erratum 764369 only applies to the level 1 cache.
* bsp/arm: Consistenly same handling for flushingRalf Kirchner2014-04-171-2/+2
| | | | | It is importeant to consistently apply the same handling for flushing within level 2 and level 1 cache handling. In this case now both handling use clean and invalidate.
* bsp/arm: RTEMS_SMP to arm erratum 764369 detectionRalf Kirchner2014-04-173-10/+8
| | | | Move the RTEMS_SMP conditional compilation to the detection method of arm erratum 764369
* bsp/arm: Erratum 764369 after enabling SCURalf Kirchner2014-04-171-1/+1
| | | | Execute the SCU part of the workaround of arm erratum 764368 after the SCU was enabled.
* bsp/arm: Correct detection of arm erratum 764368Ralf Kirchner2014-04-171-0/+1
|
* bsp/arm: Cleanup L1 cacheRalf Kirchner2014-04-171-2/+2
|
* libchip: Correct error handling in dwmac driverRalf Kirchner2014-04-171-11/+4
| | | | By fault an rtems_status_code has been expected instead of an errno error number.
* libchip: Reduce tx interruptsRalf Kirchner2014-04-174-222/+262
| | | | | | | Reduce number of packet transmitted interrupts by using the interrupt mechanism only if we run out of DMA descriptors. Under normal conditions regaining DMA descriptors, mbufs and clusters is handled via a counter.
* libchip: CleanupRalf Kirchner2014-04-171-2/+2
|
* libchip: Improve handling of DMA suspendsRalf Kirchner2014-04-171-0/+1
| | | | Reset the corresponding DMA status bit
* bsp/altera-cyclone-v: CleanupRalf Kirchner2014-04-171-2/+0
|
* bsp/altera-cyclone-v: Change console baud rateRalf Kirchner2014-04-171-1/+1
| | | | | | The baud rate of the altera cyclone-V U-Boot can not be changed at the u-Boot console prompt. Thus we use the same baud rate as the U-Boot for the BSP.
* score: Clarify TLS supportSebastian Huber2014-04-171-1/+1
|
* bsp/qoriq: SMP support for IRQ supportSebastian Huber2014-04-161-8/+11
|
* bsps/powerpc: SMP support for SPR functionsSebastian Huber2014-04-161-19/+19
| | | | | These registers are local to a processor, there is no need to use SMP locks here.
* libchip: SMP support for NS16550Sebastian Huber2014-04-161-19/+22
|
* bsps/powerpc: SMP support for one TSEC driverSebastian Huber2014-04-151-13/+16
|
* score: Add clustered/partitioned schedulingSebastian Huber2014-04-151-1/+7
| | | | | | | | | | | | | | | Clustered/partitioned scheduling helps to control the worst-case latencies in the system. The goal is to reduce the amount of shared state in the system and thus prevention of lock contention. Modern multi-processor systems tend to have several layers of data and instruction caches. With clustered/partitioned scheduling it is possible to honour the cache topology of a system and thus avoid expensive cache synchronization traffic. We have clustered scheduling in case the set of processors of a system is partitioned into non-empty pairwise-disjoint subsets. These subsets are called clusters. Clusters with a cardinality of one are partitions. Each cluster is owned by exactly one scheduler instance.
* score: SMP initialization changesSebastian Huber2014-04-145-68/+94
| | | | | | | | | | | | | | | | | Add and use _CPU_SMP_Start_processor(). Add and use _CPU_SMP_Finalize_initialization(). This makes most _CPU_SMP_Initialize() functions a bit simpler since we can calculate the minimum value of the count of processors requested by the application configuration and the count of physically or virtually available processors in the high-level code. The CPU port has now the ability to signal a processor start failure. With the support for clustered/partitioned scheduling the presence of particular processors can be configured to be optional or mandatory. There will be a fatal error only in case mandatory processors are not present. The CPU port may use a timeout to monitor the start of a processor.
* sparc: Use __leon__ multilib defineSebastian Huber2014-04-141-1/+2
|
* sparc64/niagara: add bsp_fatal_handler to terminate executionGedare Bloom2014-04-125-2/+351
| | | | Terminates the execution of niagara BSP when running in gem5.
* rtems: Rename rtems_smp_get_current_processor()Sebastian Huber2014-04-112-2/+2
| | | | | | | Rename rtems_smp_get_current_processor() in rtems_get_current_processor(). Make rtems_get_current_processor() a function in uni-processor configurations to enable ABI compatibility with SMP configurations.
* rtems: Rename rtems_smp_get_processor_count()Sebastian Huber2014-04-111-1/+1
| | | | | | Rename rtems_smp_get_processor_count() in rtems_get_processor_count(). Make rtems_get_processor_count() a function in uni-processor configurations to enable ABI compatibility with SMP configurations.
* sparc/shared/.../linkcmds.base: Correct C++ supportJoel Sherrill2014-04-041-7/+6
| | | | Add KEEP() for .eh_frame*, .ctor*, and .dtor*.
* leon2 ckinit.c, console.c: Comment clean upJoel Sherrill2014-04-032-26/+5
|
* leon2/Makefile.am: Change to one file per lineJoel Sherrill2014-04-031-7/+16
|
* erc32/Makefile.am: Change to one file per lineJoel Sherrill2014-04-031-7/+17
|
* psim/console/console-io.c: Comment clean upJoel Sherrill2014-04-031-1/+3
|
* sim68000/console/conscfg.c: Comment clean upJoel Sherrill2014-04-031-2/+0
|
* h8sim/console/console-io.c: Comment clean upJoel Sherrill2014-04-031-1/+3
|
* bsps/powerpc: Fix linker command filesSebastian Huber2014-04-014-16/+8
|
* bsps/powerpc: PR757: Fix PPC_IRQ_TRACE for ppc601Sebastian Huber2014-04-011-0/+1
| | | | We could probably also remove the ppc601 support entirely.
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-06 08:42:29 +0000