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* bsp/tms570: include package balls and PINMMR registers mapping for ↵Pavel Pisa2016-10-022-0/+700
| | | | TMS570LS3135ZWT chip.
* bsps/arm: Export bsp_start_hook_0_done symbol from ARM start.S.Pavel Pisa2016-10-021-0/+1
| | | | | | | | The symbol can be used by bsp_start_hook_0 when complete RAM memory is initialization and overwritten during BSP self-test. The test overwrites even memory used to store return address / link register and regular resturn from bsp_start_hook_0 is not possible then.
* arm/raspberrypi: minimized mainline patch move MMU in front of application ↵Pavel Pisa2016-10-022-3/+4
| | | | | | | | | | | | | | | | image and correct RPi2 boot on 4.11 branch. This is minimized version of mainline patch arm/raspberrypi: move MMU in front of application image to respect variable memory size. plus correction which has been part of other mainline patches. This is end of series which allows 4.11 to boot on Raspberry Pi. Closes #2782 Closes #2783
* arm/raspberrypi: change interrupt dispatch and enable to generic vector id ↵Pavel Pisa2016-10-022-43/+94
| | | | | | | | | | based approach. Using conditional branches to find bits is extremely inefficient and for asynchronous delivery of different interrupt sources lead to total confusion of branch prediction unit. Updates #2783
* arm/raspberrypi: remove duplicate setup of IRQ handler in the main ARM ↵Pavel Pisa2016-10-022-21/+0
| | | | | | | | | | | | | | | | | | | | | | | | | exception table. Exception table setup is processed by common CPU architecture support. For ARM architecture, it can be found in the file rtems/c/src/lib/libbsp/arm/shared/start/start.S and ends by bsp_vector_table_copy_done label. The actual tabel content can be found at bsp_start_vector_table_begin For ARMv7-A and even other variant with hypervisor mode support, it is even not necessary to copy table to address 0 at all because CP15 register can be used to specify alternative table start address arm_cp15_set_vector_base_address(&)bsp_start_vector_table_begin; ARMv7-M have register to set exception table base as well. Updates #2783
* arm/raspberrypi: ensure that correct RPI_PERIPHERAL_BASE is provided by ↵Pavel Pisa2016-10-022-0/+2
| | | | | | | | | | | | | raspberrypi.h If the raspberrypi.h has been included without preceding inclussion of bsp.h then BSP_IS_RPI2 has not been set for Raspberry Pi 2 BSP variant and bad things happen later. The patch includes bspopts.h by raspberrypi.h and even includes bsp.h in critical peripherals support. Updates #2783
* arm/raspberrypi: reorder and update MMU config table to nor force RW section ↵Pavel Pisa2016-10-021-9/+22
| | | | | | | | | | | later to RO. Enable even the first megabyte of SDRAM to be cache-able after problems with stale cache content has been resolved by previous commit. Because major part of application usually fits to the first megabyte this speedups test dhrystone application by factor 40. Updates #2783
* arm/raspberrypi: Enable HYP to SVC switch for this BSP.Pavel Pisa2016-10-022-0/+7
| | | | | | | This support is required when newer firmware is used on Raspberry Pi 2 boards. Updates #2783
* bsps/arm: Support recent bootloaders starting kernel in HYP modePavel Pisa2016-10-025-7/+175
| | | | | | | | | | | | | | | | | | | | | When HYP mode is detected at startup then setup HYP mode vectors table (for future extensions) clean exceptions switching to HYP mode and switch CPU to ARM SVC mode. BSPs which want to use this support need to include next option in their configure.ac RTEMS_BSPOPTS_SET([BSP_START_IN_HYP_SUPPORT],[*],[1]) RTEMS_BSPOPTS_HELP([BSP_START_IN_HYP_SUPPORT], [Support start of BSP in ARM HYP mode]) AM_CONDITIONAL(BSP_START_IN_HYP_SUPPORT,test "$BSP_START_IN_HYP_SUPPORT" = "1") and need to include next lines in corresponding Makefile.am if BSP_START_IN_HYP_SUPPORT libbsp_a_SOURCES += ../shared/startup/bsp-start-in-hyp-support.S endif Updates #2783
* libbsp/arm: Fix ARM BSPs missing the bsp_translation_table_end symbol.Chris Johns2016-10-022-0/+2
| | | | Closes #2775.
* libbsp/arm: Add the TTB table to the default MMU set up as read/write.Chris Johns2016-10-021-0/+4
| | | | | | | This lets the table be changed at runtime for dynamic loading and debugger support. Closes #2775.
* bsps/arm: Fix basic cache support for SMPSebastian Huber2016-10-021-8/+8
| | | | | Updates #2782 Updates #2783
* bsps/arm: reorganize CP15 code to allow clean and invalidate ARMv7 cache by ↵Pavel Pisa2016-10-021-48/+60
| | | | | | | | | | level. New function arm_cp15_cache_invalidate_level and arm_cp15_cache_clean_level can be used to maintain single cache level (instruction or data). Updates #2782 Updates #2783
* bsps/arm: remove lock in arm_cp15_set_translation_table_entries().Pavel Pisa2016-10-021-9/+1
| | | | | | | | | | | | | | Protection by rtems_interrupt_disable() is incompatible with SMP build. Actual page table entries manipulation function does not need locking and disabling cache and can be run concurrently even on multiple CPUs as long as changes do not modify same region. If the function is called from more threads/CPUs to modify same region with different mapping options concurrently then there is problem at another level of virtual address space management and has to be solved by mutex or other locking at that level. Updates #2782 Updates #2783
* bsps/arm: use defines for cache type register format field.Pavel Pisa2016-10-021-9/+30
| | | | | | | | | The change documents meaning of codes and opens well defined way to use cache type format for cache examination/debugging outside of arm-cp15.h file. Updates #2782 Updates #2783
* arm/xilinx_zynq: ensure that cache is cleaned and MMU disabled when ↵Pavel Pisa2016-10-021-0/+35
| | | | | | | | | initialization starts. The u-boot loader enables the MMU plus the data and instruction caches in some versions which results in RTEMS boot failure. Closes #2774.
* arm/raspberrypi: use cache manager operations to flush/invalidate all cache ↵Pavel Pisa2016-10-021-7/+7
| | | | | | | | | | | | levels. This fix strange behavior where some stale content has been stored in level 2 cache before RTEMS has been start from U-boot which has reappeared after MMU enable and shadow vector table at start of SDRAM. Updates #2782 Updates #2783
* arm/bsps: CP15 and basic cache support entire cache clean for more ↵Pavel Pisa2016-10-023-6/+66
| | | | | | | | | | | | | | | | | | | | architecture variants now. Next cache operations should work on most of cores now rtems_cache_flush_entire_data() rtems_cache_invalidate_entire_data() rtems_cache_invalidate_entire_instruction() Instruction cache invalidate works on the first level for now only. Data cacache operations are extended to ensure flush/invalidate on all cache levels. The CP15 arm_cp15_data_cache_clean_all_levels() function extended to continue through unified levels too (ctype = 4). Updates #2782 Updates #2783
* bsps/arm: do not disable MMU during translation table management operations.Pavel Pisa2016-10-022-8/+58
| | | | | | | | | | | | | | | | | | | | | | | Disabling MMU requires complex cache flushing and invalidation operations. There is almost no way how to do that right on SMP system without stopping all other CPUs. On the other hand, there is documented sequence of operations which should be used according to ARM manual and it guarantees even distribution of maintenance operations to other cores for last generation of Cortex-A cores with multiprocessor extension. This change could require addition of appropriate entry to arm_cp15_start_mmu_config_table for some BSPs to ensure that MMU table stays accessible after MMU is enabled { .begin = (uint32_t) bsp_translation_table_base, .end = (uint32_t) bsp_translation_table_base + 0x4000, .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED } Updates #2782 Updates #2783
* bsps/arm: basic on core cache support changed to use l1 functions.Pavel Pisa2016-10-023-48/+97
| | | | | | | | | | | | | | | | | The basic data and instruction rage functions should be compatible for all ARMv4,5,6,7 functions. On the other hand, some functions are not portable, for example arm_cp15_data_cache_test_and_clean() and arm_cp15_data_cache_invalidate() for all versions and there has to be specialized version for newer cores. arm_cache_l1_properties_for_level uses CCSIDR which is not present on older chips. Actual version is only experimental, needs more changes and problem has been found on RPi1 with dlopen so there seems to be real problem. Updates #2783 Updates #2782
* bsps/arm: Change code to explicit selection of cache implementation for ARM ↵Pavel Pisa2016-10-0210-124/+190
| | | | | | | | | | | | | | | | | | | | | | | | | | BSPs. The original ARM architecture wide cache_.h is changed to dummy version for targets not implementing/enablig cache at all. The ARM targets equipped by cache should include appropriate implementation. Next options are available for now c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h basic ARM cache integrated on the CPU core directly which requires only CP15 oparations c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h support for case where ARM L2C-310 cache controller is used. It is accessible as mmaped peripheral. c/src/lib/libbsp/arm/shared/armv7m/include/cache_.h Cortex-M specific cache support Updates #2782 Updates #2783
* bsp/arm: Report correct maximal cache line length for ARM Cortex-A + L2C-310.Pavel Pisa2016-10-021-0/+4
| | | | | Updates #2782 Updates #2783
* rtems+bsps/cache: Define cache manager operations for code synchronization ↵Pavel Pisa2016-10-021-0/+42
| | | | | | | | | | | | | | | | and maximal alignment. There is need for unambiguous named and defined cache function which should be called when code is updated, loaded or is self-modifying. There should be function to obtain maximal cache line length as well. This function can and should be used for allocations which can be used for data and or code and ensures that there are no partial cache lines overlaps on start and end of allocated region. Updates #2782
* arm/score and shared: define ARM hypervisor mode and alternate vector table ↵Pavel Pisa2016-10-021-0/+30
| | | | | | | | | | | base access. The main reason for inclusion of minimum hypervisor related defines is that current ARM boards firmware and loaders (U-boot for example) start loaded operating system kernel in HYP mode to allow it take control of virtualization (Linux/KVM for example). Updates #2783
* arm/raspberrypi: ensure that RTEMS application image can be started by U-boot.Pavel Pisa2016-10-022-1/+39
| | | | | | | | | | | | | | | | | | The current versions of U-boot start kernel/RTEMS application image with instruction and data caches enabled and it sets exception base register to new address after its self-relocation. ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */ mcr p15, 0, r0, c12, c0, 0 /* Set VBAR */ Included changes in bsp_start_hook_0 restore default state to allow RTEMS image to run after startup from newer U-boot version on Raspberry Pi. Clear interrupt enable registers in interrupt controller to ensure that RTEMS starts from well defined state. Updates #2783
* bsps/arm: CP15 support for flush prefetch buffer and table base control.Pavel Pisa2016-10-021-0/+48
| | | | | Updates #2782 Updates #2783
* bsps/powerpc: Fix shared console driverSebastian Huber2016-07-191-13/+9
| | | | | | The Termios modes are now an emum. Do not use them in #if expressions. Update #2762.
* bsps/powerpc: Fix AtliVec context switchSebastian Huber2016-07-192-62/+68
| | | | | | | Properly pass the stack aligned context to _CPU_Context_switch_altivec() since _CPU_altivec_ctxt_off defined via ppc_context. Update #2761.
* bsps/powerpc: Fix AltiVec enableSebastian Huber2016-07-193-0/+3
| | | | | | | There must be an isync after the mtmsr to ensure that the AltiVec is enabled for subsequent instructions. Close #2760.
* sparc: Fix window underflow trap handlerDaniel Hellstrom2016-03-242-7/+7
| | | | | | | | | | | | The window underflow trap handler used %i5 which destroyed the %o5 of the calling context. Bug introduced by 0d3b5d47429effb350448d9e9123a67db722109f. Go back to the pre 0d3b5d47429effb350448d9e9123a67db722109f behaviour and use the two unused instructions in the trap vector to optimize a bit. Close #2651.
* score: Fix simple timecounter supportSebastian Huber2016-01-2712-122/+188
| | | | Close #2502.
* bsps/arm: Fix broken switch statementSebastian Huber2016-01-181-4/+5
| | | | Close #2530.
* Clearly mark SMP support as experimental in 4.11Sebastian Huber2016-01-111-3/+7
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* bsp/tms570: ensure that linker symbol comparison to NULL is not optimized out.Pavel Pisa2015-12-011-2/+12
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* bsp/tms570: unite code duplication in pinmux and clean SCI close per review ↵Premysl Houdek2015-11-183-18/+21
| | | | | | remarks. Signed-off-by: Premysl Houdek <kom541000@gmail.com>
* bsp/tms570: use common tms570ls3137.inc file for all board ling variants.Pavel Pisa2015-11-185-64/+24
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* bsp/tms570: separate Flash variants to one which boots directly and one for ↵Premysl Houdek2015-11-184-0/+57
| | | | | | | | | | | | boot loader. The default tms570ls3137_hdk variant is for building RTEMS application image starting directly from start of Flash. Variant tms570ls3137_hdk_with_loader skips 256kB at start of Flash to allow use with application loader. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* bsp/tms570: use POM only when application image does not start at address 0.Pavel Pisa2015-11-187-14/+159
| | | | | | | | | | | | | | | | | | | | | Parameters overlay module is initialized and cleared first. It is used later to replace exception target vectors only if that is required. The application loader code with CPU and SDRAM setup code has to provide well defined pattern of instructions at addresses 0x00000000 and 0x0000001f, because only data read accesses can be processed reliably by POM. The expected instruction pattern can be seen in the next example https://github.com/hornmich/tms570ls3137-hdk-sdram/blob/master/SDRAM_SCI_configuration/source/sys_intvecs.asm Comments with detailed description of code, background and reasons for selected approach have been included in TMS570 bsp startup code. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Signed-off-by: Premysl Houdek <kom541000@gmail.com>
* bsp/tms570: updated reserved space for vector overlay in internal RAMPremysl Houdek2015-11-183-4/+6
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* bsp/tms570: fixed sci driver freeze when closing terminal bugPremysl Houdek2015-11-181-3/+5
| | | | | | tms570_sci_interrupt_last_close: do not wait for old data transmit. Signed-off-by: Premysl Houdek <kom541000@gmail.com>
* bsp/tms570: Pinmux support and EMAC pin definition addedPremysl Houdek2015-11-184-1/+216
| | | | Signed-off-by: Premysl Houdek <kom541000@gmail.com>
* bsp/tms570: EMAC control header file corrected and EMAC interrupt vector addedPremysl Houdek2015-11-186-236/+295
| | | | | Signed-off-by: Premysl Houdek <kom541000@gmail.com> Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* sparc: Fix context switch on SMPDaniel Cederman2015-11-171-17/+14
| | | | | | | | | | | | | | | | | | We must not load registers (e.g. PSR) from the heir context area before the heir stopped execution. With this patch the write to PSR is divided into two steps. We first update the current window pointer and then we restore the status registers and enable traps. This allows us to move the first write to PSR to be before the write to WIM, as there is now no risk that we get an interrupt where the CWP and WIM would be inconsistent. We only need to make sure that we do not use any of the non-global registers or instructions that affects CWP for three instructions after the write. In the earlier code the non-global %o1 register was used right after the write to PSR, which required the use of three nop:s. Close #2472.
* Fix interrupt epilogue for ARMv7-AR and PowerPCSebastian Huber2015-11-171-13/+38
| | | | Close #2470.
* moxiesim/configure.ac: Fix typoJoel Sherrill2015-10-201-1/+1
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* h8sim-testsuite.tcfg: Add fsdosfsname01Joel Sherrill2015-10-201-0/+1
| | | | closes #2432.
* bsp/leon3: Fix Termios context usageSebastian Huber2015-10-201-8/+3
| | | | | Only the context of the console device was used and this is wrong in case more than one APBUART device is available.
* Beaglebone: fix missing clobber in inline assembly.Marcos Diaz2015-09-101-1/+7
| | | | | | | | flush_data_cache uses R0 directly but doesn't list it as a clobbered register. Compiling with -O3 made this code break, since the function that calls flush_data_cache already uses r0. closes #2416.
* various .h files: Add missing C++ extern wrappersMartin Galvan2015-09-031-0/+4
| | | | Updates #2405.
* ada-tests/support/init.c: Fix compile errors and warningsJoel Sherrill2015-08-021-12/+19
| | | | closes #2379.
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