| Commit message (Collapse) | Author | Age | Files | Lines |
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The TLS section symbols had wrong values in case of an empty TLS data
section and a nonempty TLS BSS section.
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Add new methods which deliver the cache sizes of for supported cache levels.
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This level 2 cache is a shared data and instruction cache and thus needs locking.
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Correct misalignment handling and prepare for locking.
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Correct misalignment handling and prepare for locking.
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Arm erratum 764369 only applies to the level 1 cache.
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It is importeant to consistently apply the same handling for flushing within
level 2 and level 1 cache handling. In this case now both handling use clean and invalidate.
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Move the RTEMS_SMP conditional compilation to the detection method of arm erratum 764369
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Execute the SCU part of the workaround of arm erratum 764368 after the SCU was enabled.
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The baud rate of the altera cyclone-V U-Boot can not be changed at the
u-Boot console prompt. Thus we use the same baud rate as the U-Boot for
the BSP.
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These registers are local to a processor, there is no need to use SMP
locks here.
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Clustered/partitioned scheduling helps to control the worst-case
latencies in the system. The goal is to reduce the amount of shared
state in the system and thus prevention of lock contention. Modern
multi-processor systems tend to have several layers of data and
instruction caches. With clustered/partitioned scheduling it is
possible to honour the cache topology of a system and thus avoid
expensive cache synchronization traffic.
We have clustered scheduling in case the set of processors of a system
is partitioned into non-empty pairwise-disjoint subsets. These subsets
are called clusters. Clusters with a cardinality of one are partitions.
Each cluster is owned by exactly one scheduler instance.
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Add and use _CPU_SMP_Start_processor(). Add and use
_CPU_SMP_Finalize_initialization(). This makes most
_CPU_SMP_Initialize() functions a bit simpler since we can calculate the
minimum value of the count of processors requested by the application
configuration and the count of physically or virtually available
processors in the high-level code.
The CPU port has now the ability to signal a processor start failure.
With the support for clustered/partitioned scheduling the presence of
particular processors can be configured to be optional or mandatory.
There will be a fatal error only in case mandatory processors are not
present.
The CPU port may use a timeout to monitor the start of a processor.
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Terminates the execution of niagara BSP when running in gem5.
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Rename rtems_smp_get_current_processor() in
rtems_get_current_processor(). Make rtems_get_current_processor() a
function in uni-processor configurations to enable ABI compatibility
with SMP configurations.
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Rename rtems_smp_get_processor_count() in rtems_get_processor_count().
Make rtems_get_processor_count() a function in uni-processor
configurations to enable ABI compatibility with SMP configurations.
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Add KEEP() for .eh_frame*, .ctor*, and .dtor*.
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We could probably also remove the ppc601 support entirely.
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See errata of respective chip. Some code-cleanup as well.
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Changed console driver to use interrupts instead of polling.
Change to avoid overwriting CPU32Bug interrupt vector when setting up the Sci interrupt handler.
Fixed type for boolean flag in bsp.h.
Changed mrm332.h to use 25Mhz clock.
Fixes to mrm332.cfg to use correct mcpu32 value for RTEMS_CPU_MODEL instead of m68332 which is no longer supported.
Added -mcpu=cpu32 to compiler options.
Removed broken ROM linker script and replaced broken RAM linker script with working ROM linker script.
Removed no longer required file except_vect_332_ROM.S.
Enabled 0xbeefbeef magic string in start.S to allow MRM version of CPU32Bug to auto run RTEMS.
Removed old code from start.S
Changed compiler optimization flag to optimize for size.
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Moved prototype for __gnat_install_handler and __gnat_install_handler_common to common header file. Placed header file in bsp namespace.
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