| Commit message (Collapse) | Author | Age | Files | Lines |
|
|
|
| |
Also regenerate preinstall.am. Closes #2434.
|
|
|
|
| |
updates 2254.
|
|
|
|
| |
closes #2432.
|
|
|
|
|
| |
Only the context of the console device was used and this is wrong in
case more than one APBUART device is available.
|
| |
|
| |
|
| |
|
| |
|
|
|
|
| |
See also bc820946793426dbdc450dc8bba4a15d01006182.
|
| |
|
|
|
|
|
| |
This avoids consumption of a loadable address space for the nocache
heap.
|
| |
|
| |
|
| |
|
| |
|
|
|
|
|
|
|
|
| |
According to the C11 and C++11 memory models only a read-modify-write
operation guarantees that we read the last value written in modification
order. Avoid the sequential consistent thread fence and instead use the
inter-processor interrupt to set the thread dispatch necessary
indicator.
|
| |
|
|
|
|
|
|
|
|
|
|
| |
Further documentation can be found in
https://devel.rtems.org/wiki/GSoC/2015/RaspberryPi_peripherals_and_SD_card
and test data (including sample user applications, device drivers and wiring schemes) can be found in
https://github.com/asuol/RTEMS_rpi_testing
|
| |
|
| |
|
|
|
|
|
|
|
|
| |
flush_data_cache uses R0 directly but doesn't list it as a clobbered
register. Compiling with -O3 made this code break, since the function
that calls flush_data_cache already uses r0.
closes #2416.
|
| |
|
|
|
|
| |
Close #2385.
|
|
|
|
| |
Updates #2405.
|
|
|
|
| |
GPIO Driver Development for BeagleBone Black based on the generic GPIO API
|
|
|
|
|
| |
makes rtems_gpio_bsp_get_value return uint32_t. Motivation: simplify
beagle gpio implementation for common gpio apio.
|
|
|
|
|
|
| |
Added support for the new RTEMS GPIO API functions.
Test cases can be found in https://github.com/asuol/RTEMS_rpi_testing/tree/master/GPIO
|
|
|
|
|
|
|
|
|
|
|
| |
Changes relative to the previous patch set:
- Moved GPIO pin interrupts to rtems chains, instead of a local linked list;
- Restructured the pin tracking structure, separating the interrupt information for each pin meaning that a pin without any interrupt enabled only requires 8 bytes, while keeping interrupt information (handling information, handler chain control, ...) requires 24 additional bytes (total of 32 bytes per pin with interrupts enabled);
- Added support for 'parallel' pin function assignment, allowing the function assignment to be set for multiple pins in a single GPIO hardware call. If a BSP does not support this feature it becomes a sequence of individual calls per pin. Also added support for GPIO pin groupings, allowing to write and read byte data to a series of pins which behave as a single entity;
- Added bank tracking structure to maintain the bank lock and bank level interrupt information (threaded/normal handling, interrupt counter);
- Changed GPIO settings to BSP defined constants, reducing dynamic memory allocation;
- Switched interrupt tasks for a rtems interrupt server, with the possibility of using normal interrupts (user handlers being called within ISR context).
|
|
|
|
|
| |
This would lead to link-time errors in case less specialized compiler
machine options are used, e.g. to run the GCC test suite.
|
| |
|
|
|
|
| |
Signed-off-by: Premysl Houdek <kom541000@gmail.com>
|
|
|
|
|
|
|
|
| |
there is no need to define access macros for field covering
whole registers. In addition, BSP_FLD32 does not work right
for field 32bit length.
Signed-off-by: Premysl Houdek <kom541000@gmail.com>
|
|
|
|
| |
Close #2373.
|
| |
|
|
|
|
| |
Signed-off-by: Premysl Houdek <kom541000@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The update fixes breakage of TMS570 support after Alexander Krutwig
switch of RTEMS time read to timecounter mechanism
bsps: Convert clock drivers to use a timecounter
Mechanism to specify odd (non 1 Mhz) time base update frequencies
implemented after objections of Martin Galvan.
Code is adjusted to convert RTEMS configuration parameter
microseconds_per_tick to such odd base if
TMS570_PREFERRED_TC_FREQUENCY is specified appropriately.
Signed-off-by: Premysl Houdek <kom541000@gmail.com>
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
|
|
|
|
|
|
|
|
|
|
| |
The header files are generated by script make_header.py.
Current script's version can be found at:
https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python
Registers offsets and fields have been extracted from reference manual.
Signed-off-by: Premysl Houdek <kom541000@gmail.com>
|
|
|
|
| |
These files were left after running the script in the previous patch.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This was done by the following script run from libbsp:
find * -name bsp.h | xargs -e grep -l "#ifndef.*_BSP_H" | while read b
do
echo $b
cpu=`echo $b | cut -d'/' -f1 | tr '[:lower:]' '[:upper:]' `
bsp=`echo $b | cut -d'/' -f2 | tr '[:lower:]' '[:upper:]' `
g="LIBBSP_${cpu}_${bsp}_BSP_H"
# echo $g
sed -e "s/ifndef _BSP_H/ifndef ${g}/" \
-e "s/define _BSP_H/define ${g}/" \
-i $b
done
|
|
|
|
|
|
| |
The e500v1 has no support for the ATB.
Update #2369.
|
|
|
|
| |
Update #2369.
|
| |
|
| |
|
| |
|
|
|
|
|
|
|
|
| |
counter
timer interrupt was hard coded to 10 ms per tick.
Fix uses the setting of CONFIGURE_MICROSECONDS_PER_TICK to compute the correct start value for the counter
See for more information: http://permalink.gmane.org/gmane.os.rtems.user/22691
|
| |
|
|
|
|
|
|
| |
This was the only configure.ac file with bspopts.h present in
AC_CONFIG_FILES(). This somehow prevented the generation of this file
leading to build errors for this BSP.
|
| |
|
|
|
|
|
| |
Drop the <rtems/score/percpu.h> include since this file exposes a lot of
implementation details.
|
| |
|