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CONFIGURE_INTERRUPT_STACK_SIZE
closes #2801.
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startup and selftest.
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HalCoGen generated files.
The configuration is specific for TMS570LS3137 based HDK.
Pins configuration can be easily changed in
rtems/c/src/lib/libbsp/arm/tms570/hwinit/init_pinmux.c
file.
The list tms570_selftest_par_list in the file
rtems/c/src/lib/libbsp/arm/tms570/hwinit/bspstarthooks-hwinit.c
specifies peripherals which health status is examined
by parity self-test at BSP start-up. It can be easily
modified for other TMS570 family members variants same
as the selection of other tests in bspstarthooks-hwinit.c.
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Generated header file ti_herc/reg_spi.h contains complete registers
and fields set for Ti MibSPI peripheral.
Care has to be taken that only TMS570_SPI1, TMS570_SPI3 and TMS570_SPI5
are of this complete multibuffer type. TMS570_SPI2 and TMS570_SPI4
have substantial part of registers removed but else they are compatible.
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of character Tx.
The rtems_monitor_task() setups/updates termios attributes
of the opened TTY and if there is ongoing some other output
it leads to the stuck.
It would be better to use some termios API function which
would call drainOutput() in rtems/cpukit/libcsupport/src/termios.c.
But functionality is not accessible outside of core termios
implementation.
The loop waiting for last character to be sent has to be there anyway
because hardware does not provide Tx machine/shift register empty
interrupt.
Closes #2794
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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clear of alt outputs.
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TMS570LS3135ZWT chip.
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The symbol can be used by bsp_start_hook_0 when complete
RAM memory is initialization and overwritten during BSP
self-test. The test overwrites even memory used to store
return address / link register and regular resturn from
bsp_start_hook_0 is not possible then.
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image and correct RPi2 boot on 4.11 branch.
This is minimized version of mainline patch
arm/raspberrypi: move MMU in front of application image to respect variable memory size.
plus correction which has been part of other mainline patches.
This is end of series which allows 4.11 to boot on Raspberry Pi.
Closes #2782
Closes #2783
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based approach.
Using conditional branches to find bits is extremely inefficient
and for asynchronous delivery of different interrupt sources
lead to total confusion of branch prediction unit.
Updates #2783
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exception table.
Exception table setup is processed by common CPU architecture support.
For ARM architecture, it can be found in the file
rtems/c/src/lib/libbsp/arm/shared/start/start.S
and ends by bsp_vector_table_copy_done label.
The actual tabel content can be found at
bsp_start_vector_table_begin
For ARMv7-A and even other variant with hypervisor mode support,
it is even not necessary to copy table to address 0 at all
because CP15 register can be used to specify alternative
table start address
arm_cp15_set_vector_base_address(&)bsp_start_vector_table_begin;
ARMv7-M have register to set exception table base as well.
Updates #2783
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raspberrypi.h
If the raspberrypi.h has been included without preceding inclussion
of bsp.h then BSP_IS_RPI2 has not been set for Raspberry Pi 2
BSP variant and bad things happen later.
The patch includes bspopts.h by raspberrypi.h and even includes
bsp.h in critical peripherals support.
Updates #2783
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later to RO.
Enable even the first megabyte of SDRAM to be cache-able after
problems with stale cache content has been resolved by previous commit.
Because major part of application usually fits to the first
megabyte this speedups test dhrystone application by factor 40.
Updates #2783
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This support is required when newer firmware is used on
Raspberry Pi 2 boards.
Updates #2783
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When HYP mode is detected at startup then setup HYP mode
vectors table (for future extensions) clean exceptions
switching to HYP mode and switch CPU to ARM SVC mode.
BSPs which want to use this support need to include next option
in their configure.ac
RTEMS_BSPOPTS_SET([BSP_START_IN_HYP_SUPPORT],[*],[1])
RTEMS_BSPOPTS_HELP([BSP_START_IN_HYP_SUPPORT], [Support start of BSP in ARM HYP mode])
AM_CONDITIONAL(BSP_START_IN_HYP_SUPPORT,test "$BSP_START_IN_HYP_SUPPORT" = "1")
and need to include next lines in corresponding Makefile.am
if BSP_START_IN_HYP_SUPPORT
libbsp_a_SOURCES += ../shared/startup/bsp-start-in-hyp-support.S
endif
Updates #2783
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Closes #2775.
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This lets the table be changed at runtime for dynamic loading and
debugger support.
Closes #2775.
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Updates #2782
Updates #2783
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level.
New function arm_cp15_cache_invalidate_level and arm_cp15_cache_clean_level
can be used to maintain single cache level (instruction or data).
Updates #2782
Updates #2783
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Protection by rtems_interrupt_disable() is incompatible with SMP build.
Actual page table entries manipulation function does not need locking
and disabling cache and can be run concurrently even on multiple
CPUs as long as changes do not modify same region. If the function
is called from more threads/CPUs to modify same region with different
mapping options concurrently then there is problem at another level
of virtual address space management and has to be solved by mutex
or other locking at that level.
Updates #2782
Updates #2783
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The change documents meaning of codes and opens
well defined way to use cache type format for cache
examination/debugging outside of arm-cp15.h file.
Updates #2782
Updates #2783
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initialization starts.
The u-boot loader enables the MMU plus the data and instruction caches
in some versions which results in RTEMS boot failure.
Closes #2774.
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levels.
This fix strange behavior where some stale content has been
stored in level 2 cache before RTEMS has been start from U-boot
which has reappeared after MMU enable and shadow vector
table at start of SDRAM.
Updates #2782
Updates #2783
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architecture variants now.
Next cache operations should work on most of cores now
rtems_cache_flush_entire_data()
rtems_cache_invalidate_entire_data()
rtems_cache_invalidate_entire_instruction()
Instruction cache invalidate works on the first level for now only.
Data cacache operations are extended to ensure flush/invalidate
on all cache levels.
The CP15 arm_cp15_data_cache_clean_all_levels() function extended
to continue through unified levels too (ctype = 4).
Updates #2782
Updates #2783
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Disabling MMU requires complex cache flushing and invalidation
operations. There is almost no way how to do that right
on SMP system without stopping all other CPUs. On the other hand,
there is documented sequence of operations which should be used
according to ARM manual and it guarantees even distribution
of maintenance operations to other cores for last generation
of Cortex-A cores with multiprocessor extension.
This change could require addition of appropriate entry
to arm_cp15_start_mmu_config_table for some BSPs to ensure
that MMU table stays accessible after MMU is enabled
{
.begin = (uint32_t) bsp_translation_table_base,
.end = (uint32_t) bsp_translation_table_base + 0x4000,
.flags = ARMV7_MMU_DATA_READ_WRITE_CACHED
}
Updates #2782
Updates #2783
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The basic data and instruction rage functions should be compatible
for all ARMv4,5,6,7 functions. On the other hand, some functions
are not portable, for example arm_cp15_data_cache_test_and_clean()
and arm_cp15_data_cache_invalidate() for all versions and there
has to be specialized version for newer cores.
arm_cache_l1_properties_for_level uses CCSIDR which is not present
on older chips.
Actual version is only experimental, needs more changes
and problem has been found on RPi1 with dlopen so there seems
to be real problem.
Updates #2783
Updates #2782
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BSPs.
The original ARM architecture wide cache_.h is changed to dummy version
for targets not implementing/enablig cache at all.
The ARM targets equipped by cache should include
appropriate implementation.
Next options are available for now
c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h
basic ARM cache integrated on the CPU core directly
which requires only CP15 oparations
c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
support for case where ARM L2C-310 cache controller
is used. It is accessible as mmaped peripheral.
c/src/lib/libbsp/arm/shared/armv7m/include/cache_.h
Cortex-M specific cache support
Updates #2782
Updates #2783
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Updates #2782
Updates #2783
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and maximal alignment.
There is need for unambiguous named and defined cache function
which should be called when code is updated, loaded
or is self-modifying.
There should be function to obtain maximal cache line length
as well. This function can and should be used for allocations
which can be used for data and or code and ensures that
there are no partial cache lines overlaps on start and
end of allocated region.
Updates #2782
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base access.
The main reason for inclusion of minimum hypervisor related defines
is that current ARM boards firmware and loaders (U-boot for example)
start loaded operating system kernel in HYP mode to allow it take
control of virtualization (Linux/KVM for example).
Updates #2783
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The current versions of U-boot start kernel/RTEMS application image
with instruction and data caches enabled and it sets exception
base register to new address after its self-relocation.
ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
mcr p15, 0, r0, c12, c0, 0 /* Set VBAR */
Included changes in bsp_start_hook_0 restore default state to
allow RTEMS image to run after startup from newer U-boot version
on Raspberry Pi.
Clear interrupt enable registers in interrupt controller
to ensure that RTEMS starts from well defined state.
Updates #2783
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Updates #2782
Updates #2783
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The Termios modes are now an emum. Do not use them in #if expressions.
Update #2762.
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Properly pass the stack aligned context to _CPU_Context_switch_altivec()
since _CPU_altivec_ctxt_off defined via ppc_context.
Update #2761.
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There must be an isync after the mtmsr to ensure that the AltiVec is
enabled for subsequent instructions.
Close #2760.
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The window underflow trap handler used %i5 which destroyed the %o5 of
the calling context. Bug introduced by
0d3b5d47429effb350448d9e9123a67db722109f.
Go back to the pre 0d3b5d47429effb350448d9e9123a67db722109f behaviour
and use the two unused instructions in the trap vector to optimize a
bit.
Close #2651.
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Close #2502.
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Close #2530.
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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remarks.
Signed-off-by: Premysl Houdek <kom541000@gmail.com>
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Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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boot loader.
The default tms570ls3137_hdk variant is for building RTEMS
application image starting directly from start of Flash.
Variant tms570ls3137_hdk_with_loader skips 256kB at start
of Flash to allow use with application loader.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
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Parameters overlay module is initialized and cleared first.
It is used later to replace exception target vectors
only if that is required.
The application loader code with CPU and SDRAM setup
code has to provide well defined pattern of instructions
at addresses 0x00000000 and 0x0000001f, because only data
read accesses can be processed reliably by POM. The expected
instruction pattern can be seen in the next example
https://github.com/hornmich/tms570ls3137-hdk-sdram/blob/master/SDRAM_SCI_configuration/source/sys_intvecs.asm
Comments with detailed description of code, background
and reasons for selected approach have been included
in TMS570 bsp startup code.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Signed-off-by: Premysl Houdek <kom541000@gmail.com>
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tms570_sci_interrupt_last_close: do not wait for old data transmit.
Signed-off-by: Premysl Houdek <kom541000@gmail.com>
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Signed-off-by: Premysl Houdek <kom541000@gmail.com>
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