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* Updated.Joel Sherrill1999-11-111-4/+15
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* Removed reaching "up and over" to install BSP header files.Joel Sherrill1999-11-093-6/+3
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* Added #define to make this file exactly like its siblings in mpc821Joel Sherrill1999-11-091-1/+2
| | | | and mpc860 directories.
* Removed "up and over" into libbsp/.../include.Joel Sherrill1999-11-092-3/+1
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* Moved include files to hppa1.1 subdirectory and put their sourcesJoel Sherrill1999-11-096-10/+65
| | | | in the include directory.
* Removed runway directory and moved contents to include.Joel Sherrill1999-11-092-77/+0
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* New file. Added as part of adding a formal API to this object.Joel Sherrill1999-11-051-0/+54
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* Patch from Eric Valette <valette@crf.canon.fr> so this will buildJoel Sherrill1999-11-053-19/+14
| | | | independently of a BSP.
* This is another pass at making sure that nothing outside the BSPJoel Sherrill1999-11-0513-46/+28
| | | | | | | | | | | | unnecessarily uses any variables defined by the BSP. On this sweep, use of BSP_Configuration and Cpu_table was eliminated. A significant part of this modification was the addition of macros to access fields in the RTEMS configuration structures. This is necessary to strengthen the division between the BSP independent parts of RTEMS and the BSPs themselves. This started after comments and analysis by Ralf Corsepius <corsepiu@faw.uni-ulm.de>.
* The files in libcpu should not be directly dependent on any BSP. InJoel Sherrill1999-11-0443-102/+65
| | | | | | | | | | | particular, using bsp.h, or getting information from the BSP which should properly be obtained from RTEMS is forbidden. This is necessary to strengthen the division between the BSP independent parts of RTEMS and the BSPs themselves. This started after comments and analysis by Ralf Corsepius <corsepiu@faw.uni-ulm.de>. The changes primarily eliminated the need to include bsp.h and peeking at BSP_Configuration. The use of Cpu_table in each BSP needs to be eliminated.
* Corrected wildcard to pickup CPU model dependent library pieces.Joel Sherrill1999-11-011-4/+2
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* Patch rtems-rc-19991011-3.diff from Ralf Corsepius.Joel Sherrill1999-10-282-2/+2
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* Removed aclocal.m4 generated from aclocal macrosJoel Sherrill1999-10-061-851/+0
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* Removed configure generated from configure.inJoel Sherrill1999-10-061-2214/+0
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* Corrected build order so it was not as dependent on the mpc750 check.Joel Sherrill1999-10-062-6/+2
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* Fixed spelling error (FAMILLY --> FAMILY).Joel Sherrill1999-10-061-4/+4
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* Regenerated.Joel Sherrill1999-10-052-217/+412
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* Patch from Ralf Corsepius <corsepiu@faw.uni-ulm.de>:Joel Sherrill1999-10-041-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch below actuallly consists of two patches: 1) moving librpc to c/src/librpc similar to what has been done to librtems++ 2) reworked configure scripts, many safety and dependency checks added to aclocal/*.m4 macros + configuration fixes. To apply: mkdir c/src/librpc mkdir c/src/librpc/src cp c/src/lib/librpc/*.c c/src/librpc/src cp c/src/lib/librpc/Makefile.in c/src/librpc/src mkdir c/src/librpc/include mkdir c/src/librpc/include/rpc cp c/src/lib/include/rpc/* c/src/librpc/include/rpc patch -p1 < ../rtems-rc-19990820-7.diff rm -rf c/src/lib/librpc rm -rf c/src/lib/include/rpc ./autogen The additional checks in aclocal/*m4 macros add rather restrictive, sometimes unnecessarily restrictive constraints on the sequence of how macros can be used in a configure.in script. Adding them has let my problems with some more complicated configuration options vanish. Apparently some macros had not been in the required order . ---- Now I still get some linking errors for some cpus and bsps, esp when linking cdtest, but also at other locations: e.g. this happens for mips64orion/p4600: # make[5]: Entering directory `/lfs/poseidon/users/rtems/src/multi/build/mips64orion-rtems/c/p4600/tests/samples/hello' /opt/rtems/bin/mips64orion-rtems-gcc --pipe -B../../../../../../p4600/lib/ -specs bsp_specs -qrtems -DP4000 -DCPU_R4000 -DP3_DIAG -D_R4000 -D__mips=3 -mcpu=4600 -G0 -I../../../../../../p4600/lib/include/networking -g -Wall -ansi -fasm -O4 -fomit-frame-pointer -o o-p4600/hello.exe o-p4600/init.o ../../../../../../p4600/lib/no-dpmem.rel ../../../../../../p4600/lib/no-event.rel ../../../../../../p4600/lib/no-msg.rel ../../../../../../p4600/lib/no-mp.rel ../../../../../../p4600/lib/no-part.rel ../../../../../../p4600/lib/no-signal.rel ../../../../../../p4600/lib/no-timer.rel ../../../../../../p4600/lib/no-rtmon.rel /opt/rtems/mips64orion-rtems/lib/libc.a(dtoa.o): In function `_dtoa_r': /opt/hermes/embedded/build/build-mips64orion-tools/mips64orion-rtems/newlib/libc/stdlib/../../../../../src/newlib/libc/stdlib/dtoa.c:348: relocation truncated to fit: R_MIPS_LITERAL no symbol /opt/hermes/embedded/build/build-mips64orion-tools/mips64orion-rtems/newlib/libc/stdlib/../../../../../src/newlib/libc/stdlib/dtoa.c:348: relocation truncated to fit: R_MIPS_LITERAL no symbol /opt/hermes/embedded/build/build-mips64orion-tools/mips64orion-rtems/newlib/libc/stdlib/../../../../../src/newlib/libc/stdlib/dtoa.c:348: relocation truncated to fit: R_MIPS_LITERAL no symbol collect2: ld returned 1 exit status # mips64orion-rtems-gcc -v Reading specs from /opt/rtems/lib/gcc-lib/mips64orion-rtems/2.95.1/specs gcc version 2.95.1 19990816 (release) # mips64orion-rtems-ld -v GNU ld version 2.9.5 (with BFD 2.9.5)
* Removed.Joel Sherrill1999-10-041-0/+0
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* Regenerated.Joel Sherrill1999-10-041-1/+1
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* Applied patch rtems-rc-19990820-6.diff.gz fromJoel Sherrill1999-09-092-0/+2870
| | | | | Ralf Corsepius <corsepiu@faw.uni-ulm.de> which converted many Makefile.in's to Makefile.am's. This added a lot of files.
* Applied patch rtems-rc-19990820-6.diff.gz fromJoel Sherrill1999-09-0758-116/+155
| | | | | Ralf Corsepius <corsepiu@faw.uni-ulm.de> which converted many Makefile.in's to Makefile.am's. This added a lot of files.
* Patch from Ralf Corsepius <corsepiu@faw.uni-ulm.de>:Joel Sherrill1999-08-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | The patch below actually consists of 3 patches: 1. Addition of maintainer-mode dependencies on config.status and aclocal.m4 for autoconf toplevel Makefile.ins. These rules are taken over from automake generated Makefile.ins, i.e. they are contained in any automake generated toplevel Makefile.in. Having this patch in is at least a great releaf for me when working on RTEMS configuration :) 2. Automated support for #1 in acpolish 3. Some minor "beautifications" on Makefile.ins resulting from running acpolish. FYI: This patch has been generated by running tools/update/rtems-polish.sh -ac on the source tree and manually editing the resulting patch afterwards to work around a problem with acpolish, which still corrupts one Makefile.in - WARNING: Be careful with running acpolish! I expect this patch not to have any influence on normal users, unless they use --enable-maintainer-mode, thus merging it should be rather harmless.
* Support for MPC505 from Sergei Organov <osv@Javad.RU>. His patch wasJoel Sherrill1999-08-195-0/+314
| | | | | against 3.6.0 so was painful to merge. It should be OK but there is no guarantee and there are no BSPs in the tree to exercise it.
* Patch from Ralf Corsepius <corsepiu@faw.uni-ulm.de>:Joel Sherrill1999-07-302-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The main topic is replacing the hard-coded values for HAS_MP and HAS_RDBG in custom/*.cfg with per-bsp configuration-time autoconf checks (This is the patch I had mentioned before earlier this week). CHANGES * HAS_MP removed from custom/*.cfg, replaced with configuration time autoconf check * HAS_RDBG removed from custom/*.cfg, replaced with configuration-time autoconf check * NEW: c/src/make/bsp.cfg.in, takes configuration-time checked per-bsp values (i.e. HAS_MP, HAS_RDBG), gets installed as $(prefix)/<bsp>/make/bsp.cfg * NEW: default.cfg includes bsp.cfg - this change is backward compatible. * IMPORT_SRC: apply VPATH instead for ts_386ex/i386ex subdirectory Makefile.ins * HACK: a bug in acpolish mis-handles addtions to makefile variables which are enclosed in gmake conditionals: c/src/lib/libbsp/m68k/ods68302/start302/Makefile.in * Apply inline_dir, HAS_MP and HAS_RDBG for avoiding configuration of unneeded subdirectories in various configure.in files. * Several minor changes in Makefile.ins and configure.ins, wrt. to the order of including *.cfg and defining Makefile variables APPLYING THE PATCH: patch -p1 < rtems-rc-19990709-4.diff ./autogen
* Fixed typos.Joel Sherrill1999-07-303-6/+6
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* Patch from Charles-Antoine Gauthier <charles.gauthier@iit.nrc.ca>.Joel Sherrill1999-07-266-11/+11
| | | | | | | | | | | | | | | | | | | to address m68k-rtemself for the MVME167. Here is the rtems patch I promissed you a long time ago to enable ELF with m68k. The target name I selected is m68k-rtemself. It preserves the m68k-rtems COFF target, and is parterned after the other ELF/COFF dual targets. The mvme167.cfg file causes the -qelf flag to be used during compilation if the name of the compiler contains rtemself. This flag is used in the bsp_specs file to select the elflinkcmds file rather than the linkcmds file. The former is for ELF, the latter for COFF. Some patches are required to the mc68040 FPSP code. Some of the assembler files contain instructions that were rejected by the m68k-rtemself-as assembler. This is a minor bug in the m68k ELF assembler, I think.
* Patch from Ralf Corsepius <corsepiu@faw.uni-ulm.de>:Joel Sherrill1999-07-2654-57/+60
| | | | | | | | | | | | | | | | | | | | | A bug in acpolish made it into rtems-rc-19990709-0.diff, which unfortunately affects all Makefile.ins: * The maintainer mode conditional was erroniously applied to the dependencies of "Makefile". In case you already checked in rtems-rc-19990709-0.diff to CVS you have to check in all Makefile.ins again after applying the patch below :). Please apply the patch below as follows: patch -p1 < rtems-rc-19990709-1.diff tools/update/rtems-polish.sh -ac Note: There is no need to rerun your tests if you have used --enable-maintainer-mode to configure RTEMS, because this patch converts all Makefile.ins to the same settings as used for --enable-maintainer-mode.
* This is part of a major patch from Ralf Corsepius <corsepiu@faw.uni-ulm.de>Joel Sherrill1999-07-2654-993/+1096
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | to move RTEMS more to automake/autoconf and GNU compliance. Finally, here they are: the "big-patch" patches - merged into one big patch (~1.5MB). Sorry for the delay, but testing took much more time than I had expected - esp. reworking the acpolish script triggered many more tiny issues than I had expected (cf. below). At least, now you've got something to spend your weekend with :-. WARNINGS: * I've gone a little (??) further than I had announced before. * Several directories have been moved. * Several files have been added and removed * I have tested it with many BSPs/CPUs and a variety of permutiations of configuration flags, but not with all. * Most parts of the patch are automatically generated, however there are many tiny manual modifications. APPLYING THE PATCH: ./autogen -c mkdir tools mv c/src/exec/score/tools tools/cpu mv c/build-tools tools/build mv c/update-tools tools/update patch -p1 -E < rtems-rc-19990709-0.diff ./autogen If the patch doesn't apply to rtems-cvs, I would suggest that you should try to apply it brute-force and then to run tools/update/rtems-polish.sh -ac -am afterwards. A recursive diff between rtems-19990709 + patch and rtems-cvs + patch then should report only a few dozen significant changes to configuration files which need to be merged manually (IIRC, I did not change any source files). *** Attention: There are files to be removed, moved, copied and added in/to CVS! NEWS/CHANGES: 1. Configuration takes place in 3 stages: 1. per host (toplevel configure script), 2. per target (c/configure), 3. per bsp c/src/configure automatically triggered from ./configure and c/Makefile.am. 2. Building of subdirectory c/ takes place in c/$(target_alias) for cross-targets in c/ for native targets 3. Building of subdirectory c/src takes place in c/${target_alias}/<bsp> for cross-targets, c/<bsp> for native targets 4. c/build-tools moved to tools/build 5. c/src/exec/score/cpu/tools moved to tools/cpu (=cpu-tools split out) 6. c/update-tools moved to tools/update 7. New subdirectory c/src/make, handles files from make/ on a per BSP basis 8. Maintainer mode support: Ie. if configuring with --enable-maintainer-mode disabled (the default), then tracking of many dependencies will be disabled in Makefiles. Esp. many dependencies for auto* generated files will be switched off in Makefiles. Ie. if not using "--enable-maintainer-mode" many auto* generated files will not be updated automatically, i.e. normal users should not be required to have auto* tools anymore (untested). 9. Independent configuration scripts for / (toplevel), tools/build, tools/cpu, tools/update, c/, c/src/, c/src/exec, c/src/lib, c/src/tests, c/src/make 10. Automake support for all directories above and besides c/src 11. "preinstall" now is implemented as depth-first recursive make target 12. host compiled tools (exception bsp-tools) are accessed in location in the build tree instead of inside the build-tree when building RTEMS. 13. RTEMS_ROOT and PROJECT_ROOT now point to directories inside the build-tree - many tiny changes as consequence from this. 14. --with-cross-host support removed (offically announced obsolete by cygnus) 15. Changing the order of building libraries below c/src/lib/ 16. Former toplevel configure script broken into aclocal/*.m4 macros 17. Newlib now detected by configure macros, RTEMS_HAS_NEWLIB removed from *cfg. 18. sptables.h now generated by autoconf 19. Rules for "mkinstalldirs temporary installation tree" moved from c/Makefile to subdirectories. 20. Cpu-tools do not get installed. 21. FIX: Use ACLOCAL_AMFLAGS instead of ACLOCAL = -I ... in Makefile.ams which are in directories with own configure scripts. 22. Hardcoding BSP names into libbsp/.../tools to avoid RTEMS_BSP get overridden from the environment. 22. FIX: Handling of MP_PIECES in various Makefiles 23. FIX: Removing "::" rules from some Makefile.ins 24. FIX: File permission chaos: (-m 444 and -m 555 vs. -m 644 and -m 755) - Now all include files use -m 644. 25. Removed many gnumake-conditionals in Makefile.ins - Partially replaced with automake-conditional, partially replaced with conditionalized Makefile variables (... _yes_V) 26. Massively reworked acpolish: acpolish now parses Makefile.ins and interprets parts of the Makefile.ins. 27. FIX: Some $(wildcard $(srcdir)/*.h) macros removed / replaced with explicit lists of files in Makefile.ins. 28. FIX: Replacing MKLIB with RANLIB in Makefile.ins 29. HACK: Add preinstallation for pc386 specific $(PROJECT_RELEASE)/BootImgs directory ... many more details, I can't recall KNOWN BUGS: 1. make [debug|profile]_install do not do what they are promissing. "make [debug|profile] install" does what "make [debug|profile]_install" has been doing. Proposal: remove [debug|profile]_install 2. Dependencies between temporary installation tree and source tree are not yet handled correctly. 3. Dependencies between temporary installation tree and source tree are handled ineffencently (Using INSTALL_CHANGE instead of make dependencies) 4. RTEMS_ROOT, PROJECT_ROOT, top_builddir, RTEMS_TOPdir now are redundant. 5. The new configure scripts still are in their infancy. They contain redundant checks and might still contain bugs, too. 6. RTEMS autoconf Makefile.ins use a mixture of configuration information gathered in c/$(target_alias)/<bsp>/make and of information collected from their configure scripts. 7. make dist is not fully functional 8. Subdirectory host-/build-/target- configure options (--target, --host, --build) do not conform to Cygnus/GNU conventions. 9. Some RTEMS autoconf Makefile.in's makefile targets are not supported in automake Makefile.ams/ins (e.g. get, clobber). 10. Some automake standard targets are not propagated from toplevel and c/Makefile.am to autoconf subdirectories (eg. make dist). 11. rpcgen generated files are not part of the source-tree (Automake conventions favor supplying generated files inside the source-tree, however there is no support for rpcgen generated files in automake, cf. yacc/lex support in automake). 12. RTEMS_HAS_RDBG handling is flaky. make/*.cfg use RTEMS_HAS_RDBG per CPU, while librdb's sources can only be built per BSP. Raises the more general question whether librdbg located correctly in the source-tree. 13. All make/*cfg files are configured per cpu, currently there is no location to store per-bsp configuration information --> bsp.cfg, per aconfig.h? 14. "make install" without having run "make all" beforehand does not work. 15. handling of --enable-multiprocessing seems to be broken in make/custom/* 16. Makefile.ins still exploit many gmake features. 17. File permisson chaos on libraries (no explict -m for libraries/rels/etc). 18. mcp750 Makefiles are broken (Note: I *do* mean buggy - I am not talking about "not-conforming to conventions", here :-). 19. Dependencies between configure scripts are not handled, eg. aborting "make RTEMS_BSP=<bsp>" can leave the build-tree in an unusable state. 20. "make clean" does not delete <build-tree>/<bsp>. This is intentional for now, because rerunning "make" after "make clean" requires an explicit "make preinstall" afterwards now. This should be done automatically, but doesn't work in this case for now. To work around this problem <build-tree>/<bsp> is kept during "make clean" for now (HACK). TODO: 1. split out host-compiled bsp-tools 2. Use Cygnus/GNU standards for cross-compiling target-subdir (CC=CC_FOR_TARGET .. configure --host=${target_alias} --build=`config.guess'}), to be added to toplevel configure script after splitting out bsp-tools. 3. Exploit per cpu support directory (c/src/<cpu>)- Splitting out per-cpu libraries - Are there any? 4. Further automake support 5. Converting subdirectories into standalone / self-contained subdirectories (Esp. moving their headers to the same common root as their sources, eg. mv lib/include/rtems++ lib/librtems++/include/rtems++) - This is the main obstacle which prevents moving further towards automake. 6. Propagating values from *.cfg into Makefiles instead of propagating them at make time via Makefile-fragments (i.e. try to avoid using *.cfg). 7. Testing on cygwin host (I *do* expect cygwin specific problems). 8. The ARCH in o-$(ARCH)-$(VARIANT) build-subdirectories is not needed anymore. GENERAL ISSUES: 1. Temporary installation tree -- Ian and I seem to disagree basically. Though I think that I understand his argumentation, I do not share it. IMO, his way of using the buildtree is mis-using the build-tree, relying on an inofficial feature of RTEMS's current implementation, which doesn't even work correctly in the current build-tree, though it attempts hard to do so. From my very POV, it unnecessarily complicates the structures of the source- and build-trees. It is not supported by automake (No automatic generation for the necessary rules) and complicates the transition to automake significantly (Generating the rules with an enhanced version of acpolish could be possible). As Ian correctly pointed out, here a management decision is needed - though I don't see the need to draw this decision in short terms. 2. preinstallation generally is a sure means to spoil the structure of the source tree, IMHO (No ranting intended, I am completly serious about this one). eg. through tree dependencies. The worst problem related to this I have found in the meantime is bsp_specs. bsp_specs is part of libbsp, ie. there is *no* way to build *any* part of the source tree *without* having a BSP *preinstalled*. Note: This issue is related to issue 1., but is not identical - The difference is the change of the order make rules have to be triggered. While preinstallation triggers rules spread all over the source tree before a "make all" can be run, a temporary installation tree could also be installed by post "make all" hooks (all-local:, to be run after make all in a directory is completed) if the directories' dependencies would be a tree, 3. Stuctural dependencies between subdirectories. 4. Depth of the source tree (Prevents multilibbing and introduces many unnecessary configure scripts). 5. per cpu vs. per bsp configuration (There are no real per-cpu parts yets :-). 6. automake does not support $makefiles in AC_OUTPUT. Unlike before, we now should try to avoid RTEMS_CHECK_MAKEFILE and to hard-code as much paths to Makefiles as possible. 7. General redesign of the source tree 8. Main installation point - Changing it to ${prefix}/${target_alias}. ? Besides item 8. (which is a must, IMHO), as far as I see most of them can not be solved soon and will remain issues in the mid- to long-term :-. REMARKS: * You (as the maintainer) should always use --enable-maintainer-mode when building RTEMS to ensure that maintainer mode generated files (esp. those in c/src/make) will be updated when make/* files have changed. * Use @RTEMS_BSP@ in Makefile.ins and Makefile.ams below c/src/, $(RTEMS_BSP) or ${RTEMS_BSP} will be overridden from environment variables when using make RTEMS_BSP="....". * c/src/make is a temporary cludge until configuration issues are solved. At the moment it is configured per bsp, but contains per-target/cpu info only. Its main purpose now is to circumvent modifying make/*.cfg files, because I consider make/* to be frozen for backward compatibilty. * This patch should only affect configuration files. At least I do not remember having touched any source files. * To build the bare bsp you now need to mention it in --enable-rtemsbsp. Example: building gensh1 and sh1/bare simultaneously: ../rtems-rc-19990709-1/configure --target=sh-rtems \ --enable-rtemsbsp="bare gensh1" \ --prefix=/tmp/rtems \ --enable-bare-cpu-cflags='-DMHZ=20 -m1 -DCPU_CONSOLE_DEVNAME=\"/dev/null\"' \ --enable-bare-cpu-model=sh7032 \ --enable-maintainer-mode \ --enable-cxx make make install * The next steps in development would be to split out bsp-tools and then to change to Cygnus/GNU canonicalization conventions for building the c/ subdirectory afterwards (i.e. many standard AC_*.m4 macros could be used instead of customized versions) FINAL REMARK: The issues mentioned in the lists above sound much worser than the situation actually is. Most of them are not specific to this patch, but are also valid for the snapshot. I just wrote down what I came across when working on the patch over the last few weeks. I wouldn't be too surprised if you don't like the patch at the current point in development. I am willing to discuss details and problems, I also have no problem if you would post-pone applying this patch to times after 4.1, but rejecting it as a whole for all times would be a false management decision, IMHO. Therefore I would suggest that you, if your time constaints allow it, should at least play a little while with this patch to understand what is going on and before drawing a decision on how to handle this proposal. I know this patch is neither perfect nor complete, but I consider it to be a major breakthrough. Don't be anxious because of the size of the patch, the core of the patch is rather small, the size is mainly the side effect of some systematic cleanups inside the Makefiles (result of acpolish). Feel free to ask if you encounter problems, if you don't understand something or if you meet bugs - I am far from being perfect and am prepared to answer them. Ralf. -- Ralf Corsepius Forschungsinstitut fuer Anwendungsorientierte Wissensverarbeitung (FAW) Helmholtzstr. 16, 89081 Ulm, Germany Tel: +49/731/501-8690 mailto:corsepiu@faw.uni-ulm.de FAX: +49/731/501-999 http://www.faw.uni-ulm.de
* Patch to ease building MCP750 BSP.Joel Sherrill1999-07-231-1/+4
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* New files from Jiri Gaisler <jgais@ws.estec.esa.nl>.Joel Sherrill1999-07-093-0/+153
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* Patch from Jiri Gaisler <jgais@ws.estec.esa.nl>:Joel Sherrill1999-07-092-8/+8
| | | | | | + interrupt masking correction + FPU rev.B workaround + minor erc32 related fixes
* Patch from Eric Valette <valette@crf.canon.fr> to clean up theJoel Sherrill1999-07-0111-173/+119
| | | | previous submission.
* Another attempt at getting everything to build with the new powerpcJoel Sherrill1999-07-011-1/+1
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* Cleaned up to behave properly -- does not make a directory in theJoel Sherrill1999-07-011-2/+1
| | | | install tree and does not "cd wrapup."
* Now preinstalls header files.Joel Sherrill1999-07-011-4/+8
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* Removed mkdir of libcpu. This should have been at the top of the tree.Joel Sherrill1999-07-011-1/+0
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* Remove mkdir command. It should be at the top level of the tree.Joel Sherrill1999-07-011-1/+0
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* Removed pc386 specific command.Joel Sherrill1999-06-181-3/+0
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* This is a large patch from Eric Valette <valette@crf.canon.fr> that wasJoel Sherrill1999-06-142-0/+2537
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | described in the message following this paragraph. This patch also includes a mcp750 BSP. From valette@crf.canon.fr Mon Jun 14 10:03:08 1999 Date: Tue, 18 May 1999 01:30:14 +0200 (CEST) From: VALETTE Eric <valette@crf.canon.fr> To: joel@oarcorp.com Cc: raguet@crf.canon.fr, rtems-snapshots@oarcorp.com, valette@crf.canon.fr Subject: Questions/Suggestion regarding RTEMS PowerPC code (long) Dear knowledgeable RTEMS powerpc users, As some of you may know, I'm currently finalizing a port of RTEMS on a MCP750 Motorola board. I have done most of it but have some questions to ask before submitting the port. In order to understand some of the changes I have made or would like to make, maybe it is worth describing the MCP750 Motorola board. the MCP750 is a COMPACT PCI powerpc board with : 1) a MPC750 233 MHz processor, 2) a raven bus bridge/PCI controller that implement an OPENPIC compliant interrupt controller, 3) a VIA 82C586 PCI/ISA bridge that offers a PC compliant IO for keyboard, serial line, IDE, and the well known PC 8259 cascaded PIC interrupt architecture model, 4) a DEC 21140 Ethernet controller, 5) the PPCBUG Motorola firmware in flash, 6) A DEC PCI bridge, This architecture is common to most Motorola 60x/7xx board except that : 1) on VME board, the DEC PCI bridge is replaced by a VME chipset, 2) the VIA 82C586 PCI/ISA bridge is replaced by another bridge that is almost fully compatible with the via bridge... So the port should be a rather close basis for many 60x/7xx motorola board... On this board, I already have ported Linux 2.2.3 and use it both as a development and target board. Now the questions/suggestions I have : 1) EXCEPTION CODE ------------------- As far as I know exceptions on PPC are handled like interrupts. I dislike this very much as : a) Except for the decrementer exception (and maybe some other on mpc8xx), exceptions are not recoverable and the handler just need to print the full context and go to the firmware or debugger... b) The interrupt switch is only necessary for the decrementer and external interrupt (at least on 6xx,7xx). c) The full context for exception is never saved and thus cannot be used by debugger... I do understand the most important for interrupts low level code is to save the minimal context enabling to call C code for performance reasons. On non recoverable exception on the other hand, the most important is to save the maximum information concerning proc status in order to analyze the reason of the fault. At least we will need this in order to implement the port of RGDB on PPC ==> I wrote an API for connecting raw exceptions (and thus raw interrupts) for mpc750. It should be valid for most powerpc processors... I hope to find a way to make this coexist with actual code layout. The code is actually located in lib/libcpu/powerpc/mpc750 and is thus optional (provided I write my own version of exec/score/cpu/powerpc/cpu.c ...) See remark about files/directory layout organization in 4) 2) Current Implementation of ISR low level code ----------------------------------------------- I do not understand why the MSR EE flags is cleared again in exec/score/cpu/powerpc/irq_stubs.S #if (PPC_USE_SPRG) mfmsr r5 mfspr r6, sprg2 #else lwz r6,msr_initial(r11) lis r5,~PPC_MSR_DISABLE_MASK@ha ori r5,r5,~PPC_MSR_DISABLE_MASK@l and r6,r6,r5 mfmsr r5 #endif Reading the doc, when a decrementer interrupt or an external interrupt is active, the MSR EE flag is already cleared. BTW if exception/interrupt could occur, it would trash SRR0 and SRR1. In fact the code may be useful to set MSR[RI] that re-enables exception processing. BTW I will need to set other value in MSR to handle interrupts : a) I want the MSR[IR] and MSR[DR] to be set for performance reasons and also because I need DBAT support to have access to PCI memory space as the interrupt controller is in the PCI space. Reading the code, I see others have the same kind of request : /* SCE 980217 * * We need address translation ON when we call our ISR routine mtmsr r5 */ This is just another prof that even the lowest level IRQ code is fundamentally board dependent and not simply processor dependent especially when the processor use external interrupt controller because it has a single interrupt request line... Note that if you look at the PPC code high level interrupt handling code, as the "set_vector" routine that really connects the interrupt is in the BSP/startup/genpvec.c, the fact that IRQ handling is BSP specific is DE-FACTO acknowledged. I know I have already expressed this and understand that this would require some heavy change in the code but believe me you will reach a point where you will not be able to find a compatible while optimum implementation for low level interrupt handling code...) In my case this is already true... So please consider removing low level IRQ handling from exec/score/cpu/* and only let there exception handling code... Exceptions are usually only processor dependent and do not depend on external hardware mechanism to be masked or acknowledged or re-enabled (there are probably exception but ...) I have already done this for pc386 bsp but need to make it again. This time I will even propose an API. 3) R2/R13 manipulation for EABI implementation ---------------------------------------------- I do not understand the handling of r2 and r13 in the EABI case. The specification for r2 says pointer to sdata2, sbss2 section => constant. However I do not see -ffixed-r2 passed to any compilation system in make/custom/* (for info linux does this on PPC). So either this is a default compiler option when choosing powerpc-rtems and thus we do not need to do anything with this register as all the code is compiled with this compiler and linked together OR this register may be used by rtems code and then we do not need any special initialization or handling. The specification for r13 says pointer to the small data area. r13 argumentation is the same except that as far as I know the usage of the small data area requires specific compiler support so that access to variables is compiled via loading the LSB in a register and then using r13 to get full address... It is like a small memory model and it was present in IBM C compilers. => I propose to suppress any specific code for r2 and r13 in the EABI case. 4) Code layout organization (yes again :-)) ------------------------------------------- I think there are a number of design flaws in the way the code is for ppc organized and I will try to point them out. I have been beaten by this again on this new port, and was beaten last year while modifying code for pc386. a) exec/score/cpu/* vs lib/libcpu/cpu/*. I think that too many things are put in exec/score/cpu that have nothing to do with RTEMS internals but are rather related to CPU feature. This include at least : a) registers access routine (e.g GET_MSR_Value), b) interrupt masking/unmasking routines, c) cache_mngt_routine, d) mmu_mngt_routine, e) Routines to connect the raw_exception, raw_interrupt handler, b) lib/libcpu/cpu/powerpc/* With a processor family as exuberant as the powerpc family, and their well known subtle differences (604 vs 750) or unfortunately majors (8xx vs 60x) the directory structure is fine (except maybe the names that are not homogeneous) powerpc ppc421 mpc821 ... I only needed to add mpc750. But the fact that libcpu.a was not produced was a pain and the fact that this organization may duplicates code is also problematic. So, except if the support of automake provides a better solution I would like to propose something like this : powerpc mpc421 mpc821 ... mpc750 shared wrapup with the following rules : a) "shared" would act as a source container for sources that may be shared among processors. Needed files would be compiled inside the processor specific directory using the vpath Makefile mechanism. "shared" may also contain compilation code for routine that are really shared and not worth to inline... (did not found many things so far as registers access routine ARE WORTH INLINING)... In the case something is compiled there, it should create libcpushared.a b) layout under processor specific directory is free provided that 1)the result of the compilation process exports : libcpu/powerpc/"PROC"/*.h in $(PROJECT_INCLUDE)/libcpu 2) each processor specific directory creates a library called libcpuspecific.a Note that this organization enables to have a file that is nearly the same than in shared but that must differ because of processor differences... c) "wrapup" should create libcpu.a using libcpushared.a libcpuspecific.a and export it $(PROJECT_INCLUDE)/libcpu The only thing I have no ideal solution is the way to put shared definitions in "shared" and only processor specific definition in "proc". To give a concrete example, most MSR bit definition are shared among PPC processors and only some differs. if we create a single msr.h in shared it will have ifdef. If in msr.h we include libcpu/msr_c.h we will need to have it in each prowerpc specific directory (even empty). Opinions are welcomed ... Note that a similar mechanism exist in libbsp/i386 that also contains a shared directory that is used by several bsp like pc386 and i386ex and a similar wrapup mechanism... NB: I have done this for mpc750 and other processors could just use similar Makefiles... c) The exec/score/cpu/powerpc directory layout. I think the directory layout should be the same than the libcpu/powerpc. As it is not, there are a lot of ifdefs inside the code... And of course low level interrupt handling code should be removed... Besides that I do not understand why 1) things are compiled in the wrap directory, 2) some includes are moved to rtems/score, I think the "preinstall" mechanism enables to put everything in the current directory (or better in a per processor directory), 5) Interrupt handling API ------------------------- Again :-). But I think that using all the features the PIC offers is a MUST for RT system. I already explained in the prologue of this (long and probably boring) mail that the MCP750 boards offers an OPENPIC compliant architecture and that the VIA 82586 PCI/ISA bridge offers a PC compatible IO and PIC mapping. Here is a logical view of the RAVEN/VIA 82586 interrupt mapping : --------- 0 ------ | OPEN | <-----|8259| | PIC | | | 2 ------ |(RAVEN)| | | <-----|8259| | | | | | | 11 | | | | | | <---- | | | | | | | | | | | | --------- ------ | | ^ ------ | VIA PCI/ISA bridge | x -------- PCI interrupts OPENPIC offers interrupt priorities among PCI interrupts and interrupt selective masking. The 8259 offers the same kind of feature. With actual powerpc interrupt code : 1) there is no way to specify priorities among interrupts handler. This is REALLY a bad thing. For me it is as importnat as having priorities for threads... 2) for my implementation, each ISR should contain the code that acknowledge the RAVEN and 8259 cascade, modify interrupt mask on both chips, and reenable interrupt at processor level, ..., restore then on interrupt return,.... This code is actually similar to code located in some genpvec.c powerpc files, 3) I must update _ISR_Nesting_level because irq.inl use it... 4) the libchip code connects the ISR via set_vector but the libchip handler code does not contain any code to manipulate external interrupt controller hardware in order to acknoledge the interrupt or re-enable them (except for the target hardware of course) So this code is broken unless set_vector adds an additionnal prologue/epilogue before calling/returning from in order to acknoledge/mask the raven and the 8259 PICS... => Anyway already EACH BSP MUST REWRITE PART OF INTERRUPT HANDLING CODE TO CORRECTLY IMPLEMENT SET_VECTOR. I would rather offer an API similar to the one provided in libbsp/i386/shared/irq/irq.h so that : 1) Once the driver supplied methods is called the only things the ISR has to do is to worry about the external hardware that triggered the interrupt. Everything on openpic/VIA/processor would have been done by the low levels (same things as set-vector) 2) The caller will need to supply the on/off/isOn routine that are fundamental to correctly implements debuggers/performance monitoring is a portable way 3) A globally configurable interrupt priorities mechanism... I have nothing against providing a compatible set_vector just to make libchip happy but as I have already explained in other mails (months ago), I really think that the ISR connection should be handled by the BSP and that no code containing irq connection should exist the rtems generic layers... Thus I really dislike libchip on this aspect because in a long term it will force to adopt the less reach API for interrupt handling that exists (set_vector). Additional note : I think the _ISR_Is_in_progress() inline routine should be : 1) Put in a processor specific section, 2) Should not rely on a global variable, As : a) on symmetric MP, there is one interrupt level per CPU, b) On processor that have an ISP (e,g 68040), this variable is useless (MSR bit testing could be used) c) On PPC, instead of using the address of the variable via __CPU_IRQ_info.Nest_level a dedicated SPR could be used. NOTE: most of this is also true for _Thread_Dispatch_disable_level END NOTE -------- Please do not take what I said in the mail as a criticism for anyone who submitted ppc code. Any code present helped me a lot understanding PPC behavior. I just wanted by this mail to : 1) try to better understand the actual code, 2) propose concrete ways of enhancing current code by providing an alternative implementation for MCP750. I will make my best effort to try to brake nothing but this is actually hard due to the file layout organisation. 3) make understandable some changes I will probably make if joel let me do them :-) Any comments/objections are welcomed as usual. -- __ / ` Eric Valette /-- __ o _. Canon CRF (___, / (_(_(__ Rue de la touche lambert 35517 Cesson-Sevigne Cedex FRANCE Tel: +33 (0)2 99 87 68 91 Fax: +33 (0)2 99 84 11 30 E-mail: valette@crf.canon.fr
* This is a large patch from Eric Valette <valette@crf.canon.fr> that wasJoel Sherrill1999-06-1410-0/+1283
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | described in the message following this paragraph. This patch also includes a mcp750 BSP. From valette@crf.canon.fr Mon Jun 14 10:03:08 1999 Date: Tue, 18 May 1999 01:30:14 +0200 (CEST) From: VALETTE Eric <valette@crf.canon.fr> To: joel@oarcorp.com Cc: raguet@crf.canon.fr, rtems-snapshots@oarcorp.com, valette@crf.canon.fr Subject: Questions/Suggestion regarding RTEMS PowerPC code (long) Dear knowledgeable RTEMS powerpc users, As some of you may know, I'm currently finalizing a port of RTEMS on a MCP750 Motorola board. I have done most of it but have some questions to ask before submitting the port. In order to understand some of the changes I have made or would like to make, maybe it is worth describing the MCP750 Motorola board. the MCP750 is a COMPACT PCI powerpc board with : 1) a MPC750 233 MHz processor, 2) a raven bus bridge/PCI controller that implement an OPENPIC compliant interrupt controller, 3) a VIA 82C586 PCI/ISA bridge that offers a PC compliant IO for keyboard, serial line, IDE, and the well known PC 8259 cascaded PIC interrupt architecture model, 4) a DEC 21140 Ethernet controller, 5) the PPCBUG Motorola firmware in flash, 6) A DEC PCI bridge, This architecture is common to most Motorola 60x/7xx board except that : 1) on VME board, the DEC PCI bridge is replaced by a VME chipset, 2) the VIA 82C586 PCI/ISA bridge is replaced by another bridge that is almost fully compatible with the via bridge... So the port should be a rather close basis for many 60x/7xx motorola board... On this board, I already have ported Linux 2.2.3 and use it both as a development and target board. Now the questions/suggestions I have : 1) EXCEPTION CODE ------------------- As far as I know exceptions on PPC are handled like interrupts. I dislike this very much as : a) Except for the decrementer exception (and maybe some other on mpc8xx), exceptions are not recoverable and the handler just need to print the full context and go to the firmware or debugger... b) The interrupt switch is only necessary for the decrementer and external interrupt (at least on 6xx,7xx). c) The full context for exception is never saved and thus cannot be used by debugger... I do understand the most important for interrupts low level code is to save the minimal context enabling to call C code for performance reasons. On non recoverable exception on the other hand, the most important is to save the maximum information concerning proc status in order to analyze the reason of the fault. At least we will need this in order to implement the port of RGDB on PPC ==> I wrote an API for connecting raw exceptions (and thus raw interrupts) for mpc750. It should be valid for most powerpc processors... I hope to find a way to make this coexist with actual code layout. The code is actually located in lib/libcpu/powerpc/mpc750 and is thus optional (provided I write my own version of exec/score/cpu/powerpc/cpu.c ...) See remark about files/directory layout organization in 4) 2) Current Implementation of ISR low level code ----------------------------------------------- I do not understand why the MSR EE flags is cleared again in exec/score/cpu/powerpc/irq_stubs.S #if (PPC_USE_SPRG) mfmsr r5 mfspr r6, sprg2 #else lwz r6,msr_initial(r11) lis r5,~PPC_MSR_DISABLE_MASK@ha ori r5,r5,~PPC_MSR_DISABLE_MASK@l and r6,r6,r5 mfmsr r5 #endif Reading the doc, when a decrementer interrupt or an external interrupt is active, the MSR EE flag is already cleared. BTW if exception/interrupt could occur, it would trash SRR0 and SRR1. In fact the code may be useful to set MSR[RI] that re-enables exception processing. BTW I will need to set other value in MSR to handle interrupts : a) I want the MSR[IR] and MSR[DR] to be set for performance reasons and also because I need DBAT support to have access to PCI memory space as the interrupt controller is in the PCI space. Reading the code, I see others have the same kind of request : /* SCE 980217 * * We need address translation ON when we call our ISR routine mtmsr r5 */ This is just another prof that even the lowest level IRQ code is fundamentally board dependent and not simply processor dependent especially when the processor use external interrupt controller because it has a single interrupt request line... Note that if you look at the PPC code high level interrupt handling code, as the "set_vector" routine that really connects the interrupt is in the BSP/startup/genpvec.c, the fact that IRQ handling is BSP specific is DE-FACTO acknowledged. I know I have already expressed this and understand that this would require some heavy change in the code but believe me you will reach a point where you will not be able to find a compatible while optimum implementation for low level interrupt handling code...) In my case this is already true... So please consider removing low level IRQ handling from exec/score/cpu/* and only let there exception handling code... Exceptions are usually only processor dependent and do not depend on external hardware mechanism to be masked or acknowledged or re-enabled (there are probably exception but ...) I have already done this for pc386 bsp but need to make it again. This time I will even propose an API. 3) R2/R13 manipulation for EABI implementation ---------------------------------------------- I do not understand the handling of r2 and r13 in the EABI case. The specification for r2 says pointer to sdata2, sbss2 section => constant. However I do not see -ffixed-r2 passed to any compilation system in make/custom/* (for info linux does this on PPC). So either this is a default compiler option when choosing powerpc-rtems and thus we do not need to do anything with this register as all the code is compiled with this compiler and linked together OR this register may be used by rtems code and then we do not need any special initialization or handling. The specification for r13 says pointer to the small data area. r13 argumentation is the same except that as far as I know the usage of the small data area requires specific compiler support so that access to variables is compiled via loading the LSB in a register and then using r13 to get full address... It is like a small memory model and it was present in IBM C compilers. => I propose to suppress any specific code for r2 and r13 in the EABI case. 4) Code layout organization (yes again :-)) ------------------------------------------- I think there are a number of design flaws in the way the code is for ppc organized and I will try to point them out. I have been beaten by this again on this new port, and was beaten last year while modifying code for pc386. a) exec/score/cpu/* vs lib/libcpu/cpu/*. I think that too many things are put in exec/score/cpu that have nothing to do with RTEMS internals but are rather related to CPU feature. This include at least : a) registers access routine (e.g GET_MSR_Value), b) interrupt masking/unmasking routines, c) cache_mngt_routine, d) mmu_mngt_routine, e) Routines to connect the raw_exception, raw_interrupt handler, b) lib/libcpu/cpu/powerpc/* With a processor family as exuberant as the powerpc family, and their well known subtle differences (604 vs 750) or unfortunately majors (8xx vs 60x) the directory structure is fine (except maybe the names that are not homogeneous) powerpc ppc421 mpc821 ... I only needed to add mpc750. But the fact that libcpu.a was not produced was a pain and the fact that this organization may duplicates code is also problematic. So, except if the support of automake provides a better solution I would like to propose something like this : powerpc mpc421 mpc821 ... mpc750 shared wrapup with the following rules : a) "shared" would act as a source container for sources that may be shared among processors. Needed files would be compiled inside the processor specific directory using the vpath Makefile mechanism. "shared" may also contain compilation code for routine that are really shared and not worth to inline... (did not found many things so far as registers access routine ARE WORTH INLINING)... In the case something is compiled there, it should create libcpushared.a b) layout under processor specific directory is free provided that 1)the result of the compilation process exports : libcpu/powerpc/"PROC"/*.h in $(PROJECT_INCLUDE)/libcpu 2) each processor specific directory creates a library called libcpuspecific.a Note that this organization enables to have a file that is nearly the same than in shared but that must differ because of processor differences... c) "wrapup" should create libcpu.a using libcpushared.a libcpuspecific.a and export it $(PROJECT_INCLUDE)/libcpu The only thing I have no ideal solution is the way to put shared definitions in "shared" and only processor specific definition in "proc". To give a concrete example, most MSR bit definition are shared among PPC processors and only some differs. if we create a single msr.h in shared it will have ifdef. If in msr.h we include libcpu/msr_c.h we will need to have it in each prowerpc specific directory (even empty). Opinions are welcomed ... Note that a similar mechanism exist in libbsp/i386 that also contains a shared directory that is used by several bsp like pc386 and i386ex and a similar wrapup mechanism... NB: I have done this for mpc750 and other processors could just use similar Makefiles... c) The exec/score/cpu/powerpc directory layout. I think the directory layout should be the same than the libcpu/powerpc. As it is not, there are a lot of ifdefs inside the code... And of course low level interrupt handling code should be removed... Besides that I do not understand why 1) things are compiled in the wrap directory, 2) some includes are moved to rtems/score, I think the "preinstall" mechanism enables to put everything in the current directory (or better in a per processor directory), 5) Interrupt handling API ------------------------- Again :-). But I think that using all the features the PIC offers is a MUST for RT system. I already explained in the prologue of this (long and probably boring) mail that the MCP750 boards offers an OPENPIC compliant architecture and that the VIA 82586 PCI/ISA bridge offers a PC compatible IO and PIC mapping. Here is a logical view of the RAVEN/VIA 82586 interrupt mapping : --------- 0 ------ | OPEN | <-----|8259| | PIC | | | 2 ------ |(RAVEN)| | | <-----|8259| | | | | | | 11 | | | | | | <---- | | | | | | | | | | | | --------- ------ | | ^ ------ | VIA PCI/ISA bridge | x -------- PCI interrupts OPENPIC offers interrupt priorities among PCI interrupts and interrupt selective masking. The 8259 offers the same kind of feature. With actual powerpc interrupt code : 1) there is no way to specify priorities among interrupts handler. This is REALLY a bad thing. For me it is as importnat as having priorities for threads... 2) for my implementation, each ISR should contain the code that acknowledge the RAVEN and 8259 cascade, modify interrupt mask on both chips, and reenable interrupt at processor level, ..., restore then on interrupt return,.... This code is actually similar to code located in some genpvec.c powerpc files, 3) I must update _ISR_Nesting_level because irq.inl use it... 4) the libchip code connects the ISR via set_vector but the libchip handler code does not contain any code to manipulate external interrupt controller hardware in order to acknoledge the interrupt or re-enable them (except for the target hardware of course) So this code is broken unless set_vector adds an additionnal prologue/epilogue before calling/returning from in order to acknoledge/mask the raven and the 8259 PICS... => Anyway already EACH BSP MUST REWRITE PART OF INTERRUPT HANDLING CODE TO CORRECTLY IMPLEMENT SET_VECTOR. I would rather offer an API similar to the one provided in libbsp/i386/shared/irq/irq.h so that : 1) Once the driver supplied methods is called the only things the ISR has to do is to worry about the external hardware that triggered the interrupt. Everything on openpic/VIA/processor would have been done by the low levels (same things as set-vector) 2) The caller will need to supply the on/off/isOn routine that are fundamental to correctly implements debuggers/performance monitoring is a portable way 3) A globally configurable interrupt priorities mechanism... I have nothing against providing a compatible set_vector just to make libchip happy but as I have already explained in other mails (months ago), I really think that the ISR connection should be handled by the BSP and that no code containing irq connection should exist the rtems generic layers... Thus I really dislike libchip on this aspect because in a long term it will force to adopt the less reach API for interrupt handling that exists (set_vector). Additional note : I think the _ISR_Is_in_progress() inline routine should be : 1) Put in a processor specific section, 2) Should not rely on a global variable, As : a) on symmetric MP, there is one interrupt level per CPU, b) On processor that have an ISP (e,g 68040), this variable is useless (MSR bit testing could be used) c) On PPC, instead of using the address of the variable via __CPU_IRQ_info.Nest_level a dedicated SPR could be used. NOTE: most of this is also true for _Thread_Dispatch_disable_level END NOTE -------- Please do not take what I said in the mail as a criticism for anyone who submitted ppc code. Any code present helped me a lot understanding PPC behavior. I just wanted by this mail to : 1) try to better understand the actual code, 2) propose concrete ways of enhancing current code by providing an alternative implementation for MCP750. I will make my best effort to try to brake nothing but this is actually hard due to the file layout organisation. 3) make understandable some changes I will probably make if joel let me do them :-) Any comments/objections are welcomed as usual. -- __ / ` Eric Valette /-- __ o _. Canon CRF (___, / (_(_(__ Rue de la touche lambert 35517 Cesson-Sevigne Cedex FRANCE Tel: +33 (0)2 99 87 68 91 Fax: +33 (0)2 99 84 11 30 E-mail: valette@crf.canon.fr
* This is a large patch from Eric Valette <valette@crf.canon.fr> that wasJoel Sherrill1999-06-1413-1/+1229
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | described in the message following this paragraph. This patch also includes a mcp750 BSP. From valette@crf.canon.fr Mon Jun 14 10:03:08 1999 Date: Tue, 18 May 1999 01:30:14 +0200 (CEST) From: VALETTE Eric <valette@crf.canon.fr> To: joel@oarcorp.com Cc: raguet@crf.canon.fr, rtems-snapshots@oarcorp.com, valette@crf.canon.fr Subject: Questions/Suggestion regarding RTEMS PowerPC code (long) Dear knowledgeable RTEMS powerpc users, As some of you may know, I'm currently finalizing a port of RTEMS on a MCP750 Motorola board. I have done most of it but have some questions to ask before submitting the port. In order to understand some of the changes I have made or would like to make, maybe it is worth describing the MCP750 Motorola board. the MCP750 is a COMPACT PCI powerpc board with : 1) a MPC750 233 MHz processor, 2) a raven bus bridge/PCI controller that implement an OPENPIC compliant interrupt controller, 3) a VIA 82C586 PCI/ISA bridge that offers a PC compliant IO for keyboard, serial line, IDE, and the well known PC 8259 cascaded PIC interrupt architecture model, 4) a DEC 21140 Ethernet controller, 5) the PPCBUG Motorola firmware in flash, 6) A DEC PCI bridge, This architecture is common to most Motorola 60x/7xx board except that : 1) on VME board, the DEC PCI bridge is replaced by a VME chipset, 2) the VIA 82C586 PCI/ISA bridge is replaced by another bridge that is almost fully compatible with the via bridge... So the port should be a rather close basis for many 60x/7xx motorola board... On this board, I already have ported Linux 2.2.3 and use it both as a development and target board. Now the questions/suggestions I have : 1) EXCEPTION CODE ------------------- As far as I know exceptions on PPC are handled like interrupts. I dislike this very much as : a) Except for the decrementer exception (and maybe some other on mpc8xx), exceptions are not recoverable and the handler just need to print the full context and go to the firmware or debugger... b) The interrupt switch is only necessary for the decrementer and external interrupt (at least on 6xx,7xx). c) The full context for exception is never saved and thus cannot be used by debugger... I do understand the most important for interrupts low level code is to save the minimal context enabling to call C code for performance reasons. On non recoverable exception on the other hand, the most important is to save the maximum information concerning proc status in order to analyze the reason of the fault. At least we will need this in order to implement the port of RGDB on PPC ==> I wrote an API for connecting raw exceptions (and thus raw interrupts) for mpc750. It should be valid for most powerpc processors... I hope to find a way to make this coexist with actual code layout. The code is actually located in lib/libcpu/powerpc/mpc750 and is thus optional (provided I write my own version of exec/score/cpu/powerpc/cpu.c ...) See remark about files/directory layout organization in 4) 2) Current Implementation of ISR low level code ----------------------------------------------- I do not understand why the MSR EE flags is cleared again in exec/score/cpu/powerpc/irq_stubs.S #if (PPC_USE_SPRG) mfmsr r5 mfspr r6, sprg2 #else lwz r6,msr_initial(r11) lis r5,~PPC_MSR_DISABLE_MASK@ha ori r5,r5,~PPC_MSR_DISABLE_MASK@l and r6,r6,r5 mfmsr r5 #endif Reading the doc, when a decrementer interrupt or an external interrupt is active, the MSR EE flag is already cleared. BTW if exception/interrupt could occur, it would trash SRR0 and SRR1. In fact the code may be useful to set MSR[RI] that re-enables exception processing. BTW I will need to set other value in MSR to handle interrupts : a) I want the MSR[IR] and MSR[DR] to be set for performance reasons and also because I need DBAT support to have access to PCI memory space as the interrupt controller is in the PCI space. Reading the code, I see others have the same kind of request : /* SCE 980217 * * We need address translation ON when we call our ISR routine mtmsr r5 */ This is just another prof that even the lowest level IRQ code is fundamentally board dependent and not simply processor dependent especially when the processor use external interrupt controller because it has a single interrupt request line... Note that if you look at the PPC code high level interrupt handling code, as the "set_vector" routine that really connects the interrupt is in the BSP/startup/genpvec.c, the fact that IRQ handling is BSP specific is DE-FACTO acknowledged. I know I have already expressed this and understand that this would require some heavy change in the code but believe me you will reach a point where you will not be able to find a compatible while optimum implementation for low level interrupt handling code...) In my case this is already true... So please consider removing low level IRQ handling from exec/score/cpu/* and only let there exception handling code... Exceptions are usually only processor dependent and do not depend on external hardware mechanism to be masked or acknowledged or re-enabled (there are probably exception but ...) I have already done this for pc386 bsp but need to make it again. This time I will even propose an API. 3) R2/R13 manipulation for EABI implementation ---------------------------------------------- I do not understand the handling of r2 and r13 in the EABI case. The specification for r2 says pointer to sdata2, sbss2 section => constant. However I do not see -ffixed-r2 passed to any compilation system in make/custom/* (for info linux does this on PPC). So either this is a default compiler option when choosing powerpc-rtems and thus we do not need to do anything with this register as all the code is compiled with this compiler and linked together OR this register may be used by rtems code and then we do not need any special initialization or handling. The specification for r13 says pointer to the small data area. r13 argumentation is the same except that as far as I know the usage of the small data area requires specific compiler support so that access to variables is compiled via loading the LSB in a register and then using r13 to get full address... It is like a small memory model and it was present in IBM C compilers. => I propose to suppress any specific code for r2 and r13 in the EABI case. 4) Code layout organization (yes again :-)) ------------------------------------------- I think there are a number of design flaws in the way the code is for ppc organized and I will try to point them out. I have been beaten by this again on this new port, and was beaten last year while modifying code for pc386. a) exec/score/cpu/* vs lib/libcpu/cpu/*. I think that too many things are put in exec/score/cpu that have nothing to do with RTEMS internals but are rather related to CPU feature. This include at least : a) registers access routine (e.g GET_MSR_Value), b) interrupt masking/unmasking routines, c) cache_mngt_routine, d) mmu_mngt_routine, e) Routines to connect the raw_exception, raw_interrupt handler, b) lib/libcpu/cpu/powerpc/* With a processor family as exuberant as the powerpc family, and their well known subtle differences (604 vs 750) or unfortunately majors (8xx vs 60x) the directory structure is fine (except maybe the names that are not homogeneous) powerpc ppc421 mpc821 ... I only needed to add mpc750. But the fact that libcpu.a was not produced was a pain and the fact that this organization may duplicates code is also problematic. So, except if the support of automake provides a better solution I would like to propose something like this : powerpc mpc421 mpc821 ... mpc750 shared wrapup with the following rules : a) "shared" would act as a source container for sources that may be shared among processors. Needed files would be compiled inside the processor specific directory using the vpath Makefile mechanism. "shared" may also contain compilation code for routine that are really shared and not worth to inline... (did not found many things so far as registers access routine ARE WORTH INLINING)... In the case something is compiled there, it should create libcpushared.a b) layout under processor specific directory is free provided that 1)the result of the compilation process exports : libcpu/powerpc/"PROC"/*.h in $(PROJECT_INCLUDE)/libcpu 2) each processor specific directory creates a library called libcpuspecific.a Note that this organization enables to have a file that is nearly the same than in shared but that must differ because of processor differences... c) "wrapup" should create libcpu.a using libcpushared.a libcpuspecific.a and export it $(PROJECT_INCLUDE)/libcpu The only thing I have no ideal solution is the way to put shared definitions in "shared" and only processor specific definition in "proc". To give a concrete example, most MSR bit definition are shared among PPC processors and only some differs. if we create a single msr.h in shared it will have ifdef. If in msr.h we include libcpu/msr_c.h we will need to have it in each prowerpc specific directory (even empty). Opinions are welcomed ... Note that a similar mechanism exist in libbsp/i386 that also contains a shared directory that is used by several bsp like pc386 and i386ex and a similar wrapup mechanism... NB: I have done this for mpc750 and other processors could just use similar Makefiles... c) The exec/score/cpu/powerpc directory layout. I think the directory layout should be the same than the libcpu/powerpc. As it is not, there are a lot of ifdefs inside the code... And of course low level interrupt handling code should be removed... Besides that I do not understand why 1) things are compiled in the wrap directory, 2) some includes are moved to rtems/score, I think the "preinstall" mechanism enables to put everything in the current directory (or better in a per processor directory), 5) Interrupt handling API ------------------------- Again :-). But I think that using all the features the PIC offers is a MUST for RT system. I already explained in the prologue of this (long and probably boring) mail that the MCP750 boards offers an OPENPIC compliant architecture and that the VIA 82586 PCI/ISA bridge offers a PC compatible IO and PIC mapping. Here is a logical view of the RAVEN/VIA 82586 interrupt mapping : --------- 0 ------ | OPEN | <-----|8259| | PIC | | | 2 ------ |(RAVEN)| | | <-----|8259| | | | | | | 11 | | | | | | <---- | | | | | | | | | | | | --------- ------ | | ^ ------ | VIA PCI/ISA bridge | x -------- PCI interrupts OPENPIC offers interrupt priorities among PCI interrupts and interrupt selective masking. The 8259 offers the same kind of feature. With actual powerpc interrupt code : 1) there is no way to specify priorities among interrupts handler. This is REALLY a bad thing. For me it is as importnat as having priorities for threads... 2) for my implementation, each ISR should contain the code that acknowledge the RAVEN and 8259 cascade, modify interrupt mask on both chips, and reenable interrupt at processor level, ..., restore then on interrupt return,.... This code is actually similar to code located in some genpvec.c powerpc files, 3) I must update _ISR_Nesting_level because irq.inl use it... 4) the libchip code connects the ISR via set_vector but the libchip handler code does not contain any code to manipulate external interrupt controller hardware in order to acknoledge the interrupt or re-enable them (except for the target hardware of course) So this code is broken unless set_vector adds an additionnal prologue/epilogue before calling/returning from in order to acknoledge/mask the raven and the 8259 PICS... => Anyway already EACH BSP MUST REWRITE PART OF INTERRUPT HANDLING CODE TO CORRECTLY IMPLEMENT SET_VECTOR. I would rather offer an API similar to the one provided in libbsp/i386/shared/irq/irq.h so that : 1) Once the driver supplied methods is called the only things the ISR has to do is to worry about the external hardware that triggered the interrupt. Everything on openpic/VIA/processor would have been done by the low levels (same things as set-vector) 2) The caller will need to supply the on/off/isOn routine that are fundamental to correctly implements debuggers/performance monitoring is a portable way 3) A globally configurable interrupt priorities mechanism... I have nothing against providing a compatible set_vector just to make libchip happy but as I have already explained in other mails (months ago), I really think that the ISR connection should be handled by the BSP and that no code containing irq connection should exist the rtems generic layers... Thus I really dislike libchip on this aspect because in a long term it will force to adopt the less reach API for interrupt handling that exists (set_vector). Additional note : I think the _ISR_Is_in_progress() inline routine should be : 1) Put in a processor specific section, 2) Should not rely on a global variable, As : a) on symmetric MP, there is one interrupt level per CPU, b) On processor that have an ISP (e,g 68040), this variable is useless (MSR bit testing could be used) c) On PPC, instead of using the address of the variable via __CPU_IRQ_info.Nest_level a dedicated SPR could be used. NOTE: most of this is also true for _Thread_Dispatch_disable_level END NOTE -------- Please do not take what I said in the mail as a criticism for anyone who submitted ppc code. Any code present helped me a lot understanding PPC behavior. I just wanted by this mail to : 1) try to better understand the actual code, 2) propose concrete ways of enhancing current code by providing an alternative implementation for MCP750. I will make my best effort to try to brake nothing but this is actually hard due to the file layout organisation. 3) make understandable some changes I will probably make if joel let me do them :-) Any comments/objections are welcomed as usual. -- __ / ` Eric Valette /-- __ o _. Canon CRF (___, / (_(_(__ Rue de la touche lambert 35517 Cesson-Sevigne Cedex FRANCE Tel: +33 (0)2 99 87 68 91 Fax: +33 (0)2 99 84 11 30 E-mail: valette@crf.canon.fr
* Bug fix from Gunter Magin <magin@@skil.camelot.de>:Joel Sherrill1999-05-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | in libcpu/powerpc/mpc860/clock/clock.c:InstallClock() the reload value for the PIT is defined as: pit_value = (BSP_Configuration.microseconds_per_tick * Cpu_table.clicks_per_usec) - 1 ; What exactly is a tick, and what is a click? My confusion stems from the fact, that Jay defines clicks_per_usec to 1 which is correct for his configuration, where a 4MHz clock is predivided by 4 and then fed to the PIT. So I assume a "click" is just the period of the PIT input frequency. However, our HW config seems to have 32.768 kHz crystal input for PIT. Mandatory division by 4 means 8.196kHz (122usec) at the PIT. I think, the above assignment should read: pit_value = (BSP_Configuration.microseconds_per_tick / Cpu_table.clicks_per_usec) - 1; where I can define Cpu_table.clicks_per_usec in bspstart.c to 122 (clicks_per_usec). That would lead to a PIT reload value of 10000/122 - 1 = 81 to reach a 10ms "tick" period.
* Bug fix from Gunter Magin <magin@skil.camelot.de>:Joel Sherrill1999-05-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | in libcpu/powerpc/mpc860/clock/clock.c:InstallClock() the reload value for the PIT is defined as: pit_value = (BSP_Configuration.microseconds_per_tick * Cpu_table.clicks_per_usec) - 1 ; What exactly is a tick, and what is a click? My confusion stems from the fact, that Jay defines clicks_per_usec to 1 which is correct for his configuration, where a 4MHz clock is predivided by 4 and then fed to the PIT. So I assume a "click" is just the period of the PIT input frequency. However, our HW config seems to have 32.768 kHz crystal input for PIT. Mandatory division by 4 means 8.196kHz (122usec) at the PIT. I think, the above assignment should read: pit_value = (BSP_Configuration.microseconds_per_tick / Cpu_table.clicks_per_usec) - 1; where I can define Cpu_table.clicks_per_usec in bspstart.c to 122 (clicks_per_usec). That would lead to a PIT reload value of 10000/122 - 1 = 81 to reach a 10ms "tick" period.
* Patch from Erik Ivanenko <erik.ivanenko@utoronto.ca> to eliminate aJoel Sherrill1999-04-191-1/+2
| | | | warning.
* Patch from Ralf Corsepius <corsepiu@faw.uni-ulm.de>:Joel Sherrill1999-04-1946-50/+50
| | | | | | | | | | | | | | This one is an enhancement to acpolish. It replaces some Makefile variables by others variable in Makefile.ins (tries to use unique name for some variables). It therefore eases parsing Makefile.ins for further automatic Makefile.in conversions in future. To apply: cd <rtems-source-tree> sh <path-to>/rtems-rc-19990407-8.sh ./autogen
* Fixed some spacing issues.Joel Sherrill1999-04-191-4/+5
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* Addressed this bug report:Joel Sherrill1999-04-122-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | Date: Mon, 12 Apr 1999 00:38:04 +0000 From: Brendan Simon <brendan@dgs.monash.edu.au> To: Jay Monkman <jmonkman@frasca.com>, "joel@OARcorp.com" <joel@oarcorp.com> Subject: [Fwd: Goof in SMC initialize for mpc860] Nick Simon reported this bug in the eth_comm BSP sources. I see that it is still there in the latest snapshot that Joel sent me (thanks). I thought I better forward this on to you guys. Brendan. Nick.SIMON@syntegra.bt.co.uk wrote: > Sice I believe you're using the same base BSP as I am (you sent it to me) I > thought I'd mention.. > > In console-generic.c, in m860_smc_initialize, the receive buffer is malloced > and assigned to RxBd[port+3]-> buffer - it should be [port-1]. > > TTFN B
* MPC821 support and PPC patches from Andrew Bray <andy@madhouse.demon.co.uk>:Joel Sherrill1999-04-0715-1/+2953
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In c/src/exec/score/cpu/powerpc/rtems/score/ppc.h: A lot of hardware interrupts were omitted. Patch enclosed. I have also added the 821. In c/src/exec/score/cpu/powerpc/rtems/score/cpu.h: My patch adds the 821. In c/src/exec/score/cpu/powerpc/cpu.c: I have added the MPC821, and also fixed up for the missing hardware interrupts. It is also inconsistent with c/src/lib/libcpu/powerpc/mpc860/vectors/vectors.S. This has been fixed. In c/src/lib/libcpu/powerpc/mpc860/vectors/vectors.S: Fixed an inconsistency with cpu.c. I also include some new files to go with the above patches. These are the cpu library rtems-19990331/c/src/lib/libcpu/powerpc/mpc821/* and c/src/exec/score/cpu/powerpc/mpc821.h which are minor modifications of the 860 equivalents. Other comments: The various accesses to the DPRAM on the 860 are done with a linktime symbol. This could be done dynamically at run time by reading the immr register, and masking off the lower 16 bits. This takes the same amount of time as loading an address constant, and the same number of instructions as well (2). In c/src/lib/libcpu/powerpc/mpc860/console-generic/console-generic.c: This will silently fail if you attempt to use SCC1. This is only relevant if you are not using SCC1 for ethernet. This file also sets one of port B output pins for each port. This is NOT generic, it should be in the BSP specific console driver.
* Removed warning.Joel Sherrill1999-04-011-4/+6
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