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* bsps/arm: Add ARMv7-AR Generic Timer supportSebastian Huber2017-08-041-0/+322
| | | | Update #3090.
* Optional Clock_driver_support_shutdown_hardware()Sebastian Huber2017-08-042-8/+8
| | | | | Make Clock_driver_support_shutdown_hardware() optional. This avoids the atexit() support on memory constrained targets.
* bsps/powerpc: Add PPC_EXC_INTERRUPT_FRAME_SIZESebastian Huber2017-08-012-2/+4
| | | | | | Use a specific define for the interrupt exception frame size. Update #3082.
* bsps/powerpc: Rename ppc_exc_wrap_async_normalSebastian Huber2017-08-011-3/+3
| | | | | | | Rename ppc_exc_wrap_async_normal to ppc_exc_interrupt to avoid a bit of obfuscation. Update #3082.
* bsp/qoriq: Simplify fatal exceptionsSebastian Huber2017-07-313-2/+236
| | | | | | | Avoid use of small-data area, since it is not supported in the ELFv2 ABI by GCC. Update #3082.
* bsps/powerpc: Fix format specifiersSebastian Huber2017-07-311-39/+39
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* sparc: Add lazy floating point switchSebastian Huber2017-07-251-1/+125
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The SPARC ABI is a bit special with respect to the floating point context. The complete floating point context is volatile. Thus, from an ABI point of view nothing needs to be saved and restored during a context switch. Instead the floating point context must be saved and restored during interrupt processing. Historically, the deferred floating point switch was used for SPARC and the complete floating point context is saved and restored during a context switch to the new floating point unit owner. This is a bit dangerous since post-switch actions (e.g. signal handlers) and context switch extensions may silently corrupt the floating point context. The floating point unit is disabled for interrupt handlers. Thus, in case an interrupt handler uses the floating point unit then this will result in a trap (INTERNAL_ERROR_ILLEGAL_USE_OF_FLOATING_POINT_UNIT). In uniprocessor configurations, a lazy floating point context switch is used. In case an active floating point thread is interrupted (PSR[EF] == 1) and a thread dispatch is carried out, then this thread is registered as the floating point owner. When a floating point owner is present during a context switch, the floating point unit is disabled for the heir thread (PSR[EF] == 0). The floating point disabled trap checks that the use of the floating point unit is allowed and saves/restores the floating point context on demand. Update #3077.
* bsps/sparc: Fix cache supportSebastian Huber2017-07-191-4/+9
| | | | | | | Fix infinite loop in rtems_invalidate_multiple_instruction_lines(). Implement this function. Close #3080.
* sparc: Add assembly workaround for LEON3FT B2BST errataDaniel Cederman2017-07-172-0/+40
| | | | | | | | | | | | | | | This patch adds NOP instructions to prevent instruction sequences that are sensitive to the LEON3FT B2BST errata. See GRLIB-TN-0009: "LEON3FT Stale Cache Entry After Store with Data Tag Parity Error" for more information. The sequences are only modified if __FIX_LEON3FT_B2BST is defined. The patch works in conjunction with the -mfix-ut700, -mfix-gr712rc, and -mfix-ut699 GCC flags that prevents the sensitive sequences from being generated. Update #3057.
* bsps: Improve interrupt vector enable/disable APISebastian Huber2017-06-206-46/+30
| | | | | | Change bsp_interrupt_vector_enable() and bsp_interrupt_vector_disable() to not return a status code. Add bsp_interrupt_assert() and use it to validate the vector number in the vector enable/disable implementations.
* Add the i2c driver for Beaglebone BlackSichen Zhao2017-06-141-0/+136
| | | | | | | | | | Update ticket #2891 and my GSOC project add c/src/lib/libbsp/arm/beagle/i2c/bbb-i2c.c modify c/src/lib/libbsp/arm/beagle/include/i2c.h modify c/src/lib/libbsp/arm/beagle/include/bbb-gpio.h modify c/src/lib/libcpu/arm/shared/include/am335x.h modify c/src/lib/libbsp/arm/beagle/Makefile.am Now can read the EEPROM by i2c, the test application link is: https://github.com/hahchenchen/GSOC-test-application
* Simplify TLS support in context switchSebastian Huber2017-06-091-1/+0
| | | | | | There is no need to save the thread pointer in _CPU_Context_switch() since it is a thread invariant. It is initialized once in _CPU_Context_Initialize().
* Add support for IBM PowerPC 750 chip.Phong Pham2017-05-293-0/+6
| | | | Closes #3015.
* build-system: Parallel build all subdirs.Chris Johns2017-05-241-1/+1
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* sparc: Adjust assembly to improve compability with LLVMJacob Hansen2017-05-143-5/+5
| | | | | | | | | | | | | - All references of %0 changed to %g0 - 'call label,0' changed to 'call label'. According to the sparc specification call does not take any registers - '.seg "text"' changed to '.section ".text"' - the synonym stub is replaced with stb - the synonym stuh is replaced with sth
* sh/sh7750/sci/sh4uart.c: ix misleading indentation warningJoel Sherrill2017-04-241-1/+1
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* powerpc/new-exceptions/bspsupport/ppc_exc_print.c: Fix printf() format warningsJoel Sherrill2017-04-241-2/+2
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* powerpc/mpc5xx/console-generic/console-generic.c: Use updated struct termios ↵Joel Sherrill2017-04-241-2/+2
| | | | format
* libcpu/../mpc5xx/.../vectors_init.c: Using inttype macros fixes 39 format ↵Cillian O'Donnell2017-04-071-39/+41
| | | | warnings
* bsps/arm: Add Performance Monitors ExtensionSebastian Huber2017-03-271-1/+446
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* termios: Synchronize with latest FreeBSD headersKevin Kirspel2017-03-2214-33/+38
| | | | | | | | | | | Adding modified FreeBSD headers to synchronize RTEMS termios with FreeBSD. Modify termios to support dedicated input and output baud for termios structure. Updated BSPs to use dedicated input and output baud in termios structure. Updated tools to use dedicated input and output baud in termios structure. Updated termios testsuites to use dedicated input and output baud in termios structure. Close #2897.
* powerpc: Optimize AltiVec context switchSebastian Huber2017-03-072-31/+30
| | | | | | Use r8 instead of r5 to slightly optimize _CPU_Context_switch(). It is not a big deal, however, we already assume r12 is used by _CPU_Context_switch(). Treat r5 the in same way.
* powerpc: Fix AltiVec context switchSebastian Huber2017-03-071-12/+12
| | | | Update #2751.
* powerpc: Fix warningsSebastian Huber2017-03-021-1/+1
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* powerpc: Fix interrupt thread dispatchSebastian Huber2017-03-021-2/+1
| | | | Update #2751.
* bsps/powerpc: Fix warningSebastian Huber2017-02-151-2/+0
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* bsps/arm: Fix prototypeSebastian Huber2017-02-151-1/+1
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* bsps/powerpc: Fix warningsSebastian Huber2017-02-154-58/+61
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* score: Fix ARM and PowerPC context initializationSebastian Huber2016-12-021-0/+1
| | | | Update #2751.
* libdebugger: Build for ARM's without a CP15.Chris Johns2016-12-021-1/+2
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* sparc: Optimize _ISR_Handler()Sebastian Huber2016-11-281-0/+37
| | | | | | Use _Thread_Do_dispatch() instead of _Thread_Dispatch(). Restore the PSR[EF] state of the interrupted context via new system call syscall_irqdis_fp in case floating-point support is enabled.
* or1k: Avoid multiple iterations over cacheMartin Erik Werner2016-11-281-0/+27
| | | | | | | | | Previously, if the cache range operations were called with a range that was larger than the cache size, this would lead to multiple iterations over the cache, which is unnecessary. Limit this so that if the range is larger than the cache size, the operations will only iterate over the whole cache once.
* or1k: Remove secondary functions in cache managerMartin Erik Werner2016-11-281-56/+34
| | | | | | | | | | Move the code of the _CPU_OR1K_Cache_{enable,disable}_* functions into the equivalent exported _CPU_cache_{enable,disable}_* functions instead, and then delete them, in order to reduce the code indirection and aid readability. This does not touch the currently unused prefetch, writeback, and lock functions.
* or1k: Avoid excessive ISR toggle in cache managerMartin Erik Werner2016-11-282-44/+123
| | | | | | | | | | | | | | | | | Previously _ISR_Local_{disable,enable}() was executed twice for each cache line operation, and since operations over the entire cache were implemented by calling the single-line operations in a loop, this made those operations rather costly. Fix the double-toggle by calling _OR1K_mtspr() directly, and removing the now-unused corresponding _CPU_OR1K_Cache_* functions. Fix the entire-operations by moving the ISR toggle outside of the loop, and by calling _OR1K_mtspr() directly instead of the single-line operations. Also implement range functions, since otherwise the cache manager falls back on looping over the single-line operations.
* or1k: Indent & comment fix in cache.cMartin Erik Werner2016-11-281-14/+25
| | | | | | | * Fix indentation of variable declarations. * Change commented-out asm -> __asm__ to meet c99 standard if uncommented.
* or1k: Add functions for entire cache operationsMartin Erik Werner2016-11-281-3/+42
| | | | | | | | | | | | | | | Add functions for flushing and invalidating whole cache. Since we don't have system calls that can operate on anything more than a single cache line, these simply retrieves the cache size and iterates over the full size, invalidating each line. The current implementation assumes that there's only one level of cache. These changes were contributed by Antmicro under contract by ÅAC Microtec AB. Close #2602
* score: Fix interrupt profilingSebastian Huber2016-11-241-20/+13
| | | | | | | | | | Callers of _Thread_Do_dispatch() must have a valid Per_CPU_Control::Stats::thread_dispatch_disabled_instant. Call _Profiling_Outer_most_interrupt_entry_and_exit() with the interrupt stack to not exceed Per_CPU_Control::Interrupt_frame. Update #2751.
* powerpc: Fix interrupt profiling for e6500Sebastian Huber2016-11-241-1/+3
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* powerpc/mpc5xx: Rename CPU_Interrupt_frameSebastian Huber2016-11-212-4/+4
| | | | | | The MPC5XX support uses a legacy interrupt/exception infrastructure. Close #2819.
* powerpc: Use Per_CPU_Control::isr_dispatch_disableSebastian Huber2016-11-182-20/+66
| | | | Update #2751.
* score: Allow interrupts during thread dispatchSebastian Huber2016-11-181-12/+17
| | | | | | | | | Use a processor-specific interrupt frame during context switches in case the executing thread is longer executes on the processor and the heir thread is about to start execution. During this period we must not use a thread stack for interrupt processing. Update #2809.
* powerpc: Add up to date CPU_Interrupt_frameSebastian Huber2016-11-183-379/+4
| | | | | | | Rename ppc_exc_min_frame to CPU_Interrupt_frame. Move it and the corresponding defines to <rtems/score/cpuimpl.h>. Update #2809.
* powerpc: Move legacy CPU_Interrupt_frameSebastian Huber2016-11-181-0/+33
| | | | | | | The only remaining user of CPU_Interrupt_frame on PowerPC is the mpc5xx support. Move it to here. Update #2809.
* bsps/powerpc: Avoid use of CPU_Interrupt_frameSebastian Huber2016-11-181-3/+3
| | | | | | | This type is not relevant for the code since only a pointer is passed around. Update #2809.
* sparc64: Rename CPU_Minimum_stack_frameSebastian Huber2016-11-181-1/+1
| | | | | | | | Rename SPARC64-specific CPU_Minimum_stack_frame to SPARC64_Minimum_stack_frame. Rename SPARC64-specific CPU_MINIMUM_STACK_FRAME_SIZE to SPARC64_MINIMUM_STACK_FRAME_SIZE. Update #2809.
* bsps/mips: Use <libcpu/isr_entries.h>Sebastian Huber2016-11-181-0/+2
| | | | Avoid duplicate mips_vector_isr_handlers() declarations.
* powerpc: Add _CPU_Get_current_per_CPU_control()Sebastian Huber2016-11-101-1/+8
| | | | | | | | Add _CPU_Get_current_per_CPU_control() on SMP configurations. Use SPRG0 for the current per-CPU control. This reduces the code size by three instructions and is slightly faster. Update #2805.
* score: Add and use Thread_Control::is_idleSebastian Huber2016-11-092-10/+2
| | | | Update #2797.
* powerpc: Fix SMP context switchSebastian Huber2016-09-081-61/+62
| | | | | | We need the unmodified r4 for get_potential_new_heir. This partially reverts commit 8d785f72d9610fb80a65d7848404f0f7507e026c.
* bsps/arm: reorganize CP15 code to allow clean and invalidate ARMv7 cache by ↵Pavel Pisa2016-09-071-48/+60
| | | | | | | level. New function arm_cp15_cache_invalidate_level and arm_cp15_cache_clean_level can be used to maintain single cache level (instruction or data).
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