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* rtems+bsps/cache: Define cache manager operations for code synchronization ↵Pavel Pisa2016-10-021-0/+42
| | | | | | | | | | | | | | | | and maximal alignment. There is need for unambiguous named and defined cache function which should be called when code is updated, loaded or is self-modifying. There should be function to obtain maximal cache line length as well. This function can and should be used for allocations which can be used for data and or code and ensures that there are no partial cache lines overlaps on start and end of allocated region. Updates #2782
* arm/score and shared: define ARM hypervisor mode and alternate vector table ↵Pavel Pisa2016-10-021-0/+30
| | | | | | | | | | | base access. The main reason for inclusion of minimum hypervisor related defines is that current ARM boards firmware and loaders (U-boot for example) start loaded operating system kernel in HYP mode to allow it take control of virtualization (Linux/KVM for example). Updates #2783
* bsps/arm: CP15 support for flush prefetch buffer and table base control.Pavel Pisa2016-10-021-0/+48
| | | | | Updates #2782 Updates #2783
* bsps/powerpc: Fix AtliVec context switchSebastian Huber2016-07-192-62/+68
| | | | | | | Properly pass the stack aligned context to _CPU_Context_switch_altivec() since _CPU_altivec_ctxt_off defined via ppc_context. Update #2761.
* sparc: Fix window underflow trap handlerDaniel Hellstrom2016-03-241-6/+6
| | | | | | | | | | | | The window underflow trap handler used %i5 which destroyed the %o5 of the calling context. Bug introduced by 0d3b5d47429effb350448d9e9123a67db722109f. Go back to the pre 0d3b5d47429effb350448d9e9123a67db722109f behaviour and use the two unused instructions in the trap vector to optimize a bit. Close #2651.
* score: Fix simple timecounter supportSebastian Huber2016-01-271-14/+18
| | | | Close #2502.
* Fix interrupt epilogue for ARMv7-AR and PowerPCSebastian Huber2015-11-171-13/+38
| | | | Close #2470.
* bsp/mpc83xx: Update due to header guard changeSebastian Huber2015-07-172-6/+6
| | | | Close #2373.
* bsps/powerpc: Provide debug and trace symbolsSebastian Huber2015-07-081-0/+3
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* score: Simplify <rtems/system.h>Sebastian Huber2015-06-264-0/+4
| | | | | Drop the <rtems/score/percpu.h> include since this file exposes a lot of implementation details.
* score: Add Thread_Control::is_fpSebastian Huber2015-06-091-17/+1
| | | | | | | | Store the floating-point unit property in the thread control block regardless of the CPU_HARDWARE_FP and CPU_SOFTWARE_FP settings. Make sure the floating-point unit is only enabled for the corresponding multilibs. This helps targets which have a volatile only floating point context like SPARC for example.
* bsps/powerpc: Fix potential integer overflowSebastian Huber2015-05-291-1/+1
| | | | Update #2356.
* beagle bsp: RTC support for BBBragunath2015-05-282-0/+26
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* arm/s3c24xx/clock/clockdrv.c: Remove unused variable warningJoel Sherrill2015-05-211-1/+0
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* arm/lpc22xx/clock/clockdrv.c: Remove unused variable warningJoel Sherrill2015-05-211-1/+0
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* bsps: Convert clock drivers to use a timecounterAlexander Krutwig2015-05-206-122/+80
| | | | Update #2271.
* bsps/sparc: Use inline functions for cache managerSebastian Huber2015-04-273-46/+32
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* bsps/cache: Clarify range functions supportSebastian Huber2015-04-272-4/+6
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* Fix broken BSPs due to a shared cache function declaration.Hesham ALMatary2015-04-271-1/+0
| | | | | Get rid of _CPU_cache_invalidate_instruction_range declaration as it doesn't make sense here.
* score: Refactor SMP cache manager supportSebastian Huber2015-04-201-172/+51
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* Replace www.rtems.com with www.rtems.orgSebastian Huber2015-03-202-2/+2
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* rtems: Use atomic operation with correct typeDaniel Cederman2015-03-201-1/+1
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* libcpu/bfin/clock/rtc.c: Do not use rtems_clock_get()Joel Sherrill2015-03-171-2/+2
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* libcpu/powerpc/mpc8260/console-generic/console-generic.c: Include bsp.h to ↵Joel Sherrill2015-03-091-3/+1
| | | | fix warning
* sparc64: fix copyright notices.Gedare Bloom2015-02-232-14/+4
| | | | | The sparc64 port had some incorrect copyright notices affixed to source code files.
* bsps/powerpc: Fix a clock driverNick Withers2015-01-301-9/+57
| | | | | | | PowerPC Book E: Account for an extra tick period if a tick increment's pending. Close #2230.
* bsps/powerpc: Fix switch statement in CPU identSebastian Huber2015-01-231-0/+2
| | | | Close #2237.
* powerpc: Fix AltiVec VSCR save/restoreSebastian Huber2015-01-201-4/+6
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* libcpu/powerpc/mpc6xx/mmu/bat.c: Now compiles with gcc 5.xJoel Sherrill2015-01-131-12/+12
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* powerpc: AltiVec and FPU context supportSebastian Huber2015-01-137-12/+821
| | | | | | | | | | | Add AltiVec and FPU support to the Context_Control in case we use the e6500 multilib. Add PPC_MULTILIB_ALTIVEC and PPC_MULTILIB_FPU multilib defines. Add non-volatile AltiVec and FPU context to Context_Control. Add save/restore of non-volatile AltiVec and FPU to _CPU_Context_switch(). Add save/restore of volatile AltiVec and FPU context to the exception code. Adjust data cache optimizations for the new context and cache line size.
* bsps/powerpc: Use e500 exc categories for e6500Sebastian Huber2015-01-131-0/+1
| | | | This is not correct, but works for now.
* powerpc: Use PPC_HAS_FPUSebastian Huber2015-01-091-6/+6
| | | | Provide floating point context support only if PPC_HAS_FPU == 1.
* powerpc: Set PPC_DEFAULT_CACHE_LINE_SIZE for e6500Sebastian Huber2015-01-091-15/+11
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* powerpc: Use PPC_DEFAULT_CACHE_LINE_SIZESebastian Huber2015-01-091-8/+2
| | | | | Use it for the default PPC_CACHE_ALIGNMENT. Use it for PPC_STRUCTURE_ALIGNMENT.
* bsps/powerpc: ppc_exc_initialize_interrupt_stack()Sebastian Huber2015-01-092-11/+20
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* bsps/powerpc: Add TMR access macrosSebastian Huber2015-01-091-0/+28
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* bsps/powerpc: Add cache size functionsSebastian Huber2015-01-091-0/+46
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* bsps/powerpc: Delete C pre-processor warningSebastian Huber2015-01-091-2/+0
| | | | Do not warn about not implemented cache functions.
* bsps/powerpc: Support a cache alignment of 64Sebastian Huber2015-01-091-1/+8
| | | | Give the BSP the ability to define PPC_CACHE_ALIGNMENT.
* bsps/powerpc: Support e6500 indentificationSebastian Huber2015-01-092-0/+12
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* bsps/mpc83xx: Fix warningsSebastian Huber2015-01-091-4/+5
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* Use fixed-width C99 types for PowerPC in_be16() and co.Nick Withers2014-12-231-21/+22
| | | | | | Also use the const qualifier on the address pointer's target in in_*() Closes #2128
* bsp/mpc8xx: Fix warningsSebastian Huber2014-12-121-2/+0
| | | | close #2211
* bsp/mpc8xx: Fix warningsSebastian Huber2014-12-123-11/+2
| | | | close #2211
* sparc64: put each copyright on one lineGedare Bloom2014-12-083-10/+6
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* Update bug report URLSebastian Huber2014-12-0512-12/+12
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* beagle bsp: disable watchdog on am335xBen Gras2014-12-051-0/+6
| | | | | | | | | | | | On recent u-boots, the watchdog is turned on / left enabled. The Beaglebone Black rev. C ships with such a u-boot internally so any application booting from it must disable the watchdog. Therefore this change is needed to boot an RTEMS app out-of-the-box on a BBB Rev C - otherwise the user button must be held during boot (to bypass the stock uboot) or the internal uboot must be updated. To allow for a better out-of-the-box experience, we just turn off the watchdog.
* i386: doxygen and comments related to VESA real mode framebufferJan Dolezal2014-12-041-28/+37
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* SPARC: optimize IRQ enable & disableDaniel Hellstrom2014-12-042-55/+65
| | | | | | | | | | | | | | | | * Coding style cleanups. * Use OS reserved trap 0x89 for IRQ Disable * Use OS reserved trap 0x8A for IRQ Enable * Add to SPARC CPU supplement documentation This will result in faster Disable/Enable code since the system trap handler does not need to decode which function the user wants. Besides the IRQ disable/enabled can now be inline which avoids the caller to take into account that o0-o7+g1-g4 registers are destroyed by trap handler. It was also possible to reduce the interrupt trap handler by five instructions due to this.
* SPARC: optimize window underflow trapDaniel Hellstrom2014-12-021-8/+6
| | | | | | | | | | | Save five instructions on underflow handling. By using an optimized trap entry we can move instructions from the window underflow function into the trap entry vector. By setting WIM=0 and using RESTORE it is possible to move the new WIM register content from the trapped window into the to-be-restored register window. It is then possible to avoid the WIM write delay.
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