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* bsps/arm: reorganize CP15 code to allow clean and invalidate ARMv7 cache by ↵Pavel Pisa2016-10-021-48/+60
| | | | | | | | | | level. New function arm_cp15_cache_invalidate_level and arm_cp15_cache_clean_level can be used to maintain single cache level (instruction or data). Updates #2782 Updates #2783
* bsps/arm: use defines for cache type register format field.Pavel Pisa2016-10-021-9/+30
| | | | | | | | | The change documents meaning of codes and opens well defined way to use cache type format for cache examination/debugging outside of arm-cp15.h file. Updates #2782 Updates #2783
* arm/bsps: CP15 and basic cache support entire cache clean for more ↵Pavel Pisa2016-10-021-2/+42
| | | | | | | | | | | | | | | | | | | | architecture variants now. Next cache operations should work on most of cores now rtems_cache_flush_entire_data() rtems_cache_invalidate_entire_data() rtems_cache_invalidate_entire_instruction() Instruction cache invalidate works on the first level for now only. Data cacache operations are extended to ensure flush/invalidate on all cache levels. The CP15 arm_cp15_data_cache_clean_all_levels() function extended to continue through unified levels too (ctype = 4). Updates #2782 Updates #2783
* bsps/arm: do not disable MMU during translation table management operations.Pavel Pisa2016-10-021-0/+16
| | | | | | | | | | | | | | | | | | | | | | | Disabling MMU requires complex cache flushing and invalidation operations. There is almost no way how to do that right on SMP system without stopping all other CPUs. On the other hand, there is documented sequence of operations which should be used according to ARM manual and it guarantees even distribution of maintenance operations to other cores for last generation of Cortex-A cores with multiprocessor extension. This change could require addition of appropriate entry to arm_cp15_start_mmu_config_table for some BSPs to ensure that MMU table stays accessible after MMU is enabled { .begin = (uint32_t) bsp_translation_table_base, .end = (uint32_t) bsp_translation_table_base + 0x4000, .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED } Updates #2782 Updates #2783
* bsps/arm: basic on core cache support changed to use l1 functions.Pavel Pisa2016-10-021-3/+28
| | | | | | | | | | | | | | | | | The basic data and instruction rage functions should be compatible for all ARMv4,5,6,7 functions. On the other hand, some functions are not portable, for example arm_cp15_data_cache_test_and_clean() and arm_cp15_data_cache_invalidate() for all versions and there has to be specialized version for newer cores. arm_cache_l1_properties_for_level uses CCSIDR which is not present on older chips. Actual version is only experimental, needs more changes and problem has been found on RPi1 with dlopen so there seems to be real problem. Updates #2783 Updates #2782
* bsps/arm: Change code to explicit selection of cache implementation for ARM ↵Pavel Pisa2016-10-021-104/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | BSPs. The original ARM architecture wide cache_.h is changed to dummy version for targets not implementing/enablig cache at all. The ARM targets equipped by cache should include appropriate implementation. Next options are available for now c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h basic ARM cache integrated on the CPU core directly which requires only CP15 oparations c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h support for case where ARM L2C-310 cache controller is used. It is accessible as mmaped peripheral. c/src/lib/libbsp/arm/shared/armv7m/include/cache_.h Cortex-M specific cache support Updates #2782 Updates #2783
* rtems+bsps/cache: Define cache manager operations for code synchronization ↵Pavel Pisa2016-10-021-0/+42
| | | | | | | | | | | | | | | | and maximal alignment. There is need for unambiguous named and defined cache function which should be called when code is updated, loaded or is self-modifying. There should be function to obtain maximal cache line length as well. This function can and should be used for allocations which can be used for data and or code and ensures that there are no partial cache lines overlaps on start and end of allocated region. Updates #2782
* arm/score and shared: define ARM hypervisor mode and alternate vector table ↵Pavel Pisa2016-10-021-0/+30
| | | | | | | | | | | base access. The main reason for inclusion of minimum hypervisor related defines is that current ARM boards firmware and loaders (U-boot for example) start loaded operating system kernel in HYP mode to allow it take control of virtualization (Linux/KVM for example). Updates #2783
* bsps/arm: CP15 support for flush prefetch buffer and table base control.Pavel Pisa2016-10-021-0/+48
| | | | | Updates #2782 Updates #2783
* bsps/powerpc: Fix AtliVec context switchSebastian Huber2016-07-192-62/+68
| | | | | | | Properly pass the stack aligned context to _CPU_Context_switch_altivec() since _CPU_altivec_ctxt_off defined via ppc_context. Update #2761.
* sparc: Fix window underflow trap handlerDaniel Hellstrom2016-03-241-6/+6
| | | | | | | | | | | | The window underflow trap handler used %i5 which destroyed the %o5 of the calling context. Bug introduced by 0d3b5d47429effb350448d9e9123a67db722109f. Go back to the pre 0d3b5d47429effb350448d9e9123a67db722109f behaviour and use the two unused instructions in the trap vector to optimize a bit. Close #2651.
* score: Fix simple timecounter supportSebastian Huber2016-01-271-14/+18
| | | | Close #2502.
* Fix interrupt epilogue for ARMv7-AR and PowerPCSebastian Huber2015-11-171-13/+38
| | | | Close #2470.
* bsp/mpc83xx: Update due to header guard changeSebastian Huber2015-07-172-6/+6
| | | | Close #2373.
* bsps/powerpc: Provide debug and trace symbolsSebastian Huber2015-07-081-0/+3
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* score: Simplify <rtems/system.h>Sebastian Huber2015-06-264-0/+4
| | | | | Drop the <rtems/score/percpu.h> include since this file exposes a lot of implementation details.
* score: Add Thread_Control::is_fpSebastian Huber2015-06-091-17/+1
| | | | | | | | Store the floating-point unit property in the thread control block regardless of the CPU_HARDWARE_FP and CPU_SOFTWARE_FP settings. Make sure the floating-point unit is only enabled for the corresponding multilibs. This helps targets which have a volatile only floating point context like SPARC for example.
* bsps/powerpc: Fix potential integer overflowSebastian Huber2015-05-291-1/+1
| | | | Update #2356.
* beagle bsp: RTC support for BBBragunath2015-05-282-0/+26
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* arm/s3c24xx/clock/clockdrv.c: Remove unused variable warningJoel Sherrill2015-05-211-1/+0
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* arm/lpc22xx/clock/clockdrv.c: Remove unused variable warningJoel Sherrill2015-05-211-1/+0
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* bsps: Convert clock drivers to use a timecounterAlexander Krutwig2015-05-206-122/+80
| | | | Update #2271.
* bsps/sparc: Use inline functions for cache managerSebastian Huber2015-04-273-46/+32
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* bsps/cache: Clarify range functions supportSebastian Huber2015-04-272-4/+6
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* Fix broken BSPs due to a shared cache function declaration.Hesham ALMatary2015-04-271-1/+0
| | | | | Get rid of _CPU_cache_invalidate_instruction_range declaration as it doesn't make sense here.
* score: Refactor SMP cache manager supportSebastian Huber2015-04-201-172/+51
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* Replace www.rtems.com with www.rtems.orgSebastian Huber2015-03-202-2/+2
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* rtems: Use atomic operation with correct typeDaniel Cederman2015-03-201-1/+1
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* libcpu/bfin/clock/rtc.c: Do not use rtems_clock_get()Joel Sherrill2015-03-171-2/+2
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* libcpu/powerpc/mpc8260/console-generic/console-generic.c: Include bsp.h to ↵Joel Sherrill2015-03-091-3/+1
| | | | fix warning
* sparc64: fix copyright notices.Gedare Bloom2015-02-232-14/+4
| | | | | The sparc64 port had some incorrect copyright notices affixed to source code files.
* bsps/powerpc: Fix a clock driverNick Withers2015-01-301-9/+57
| | | | | | | PowerPC Book E: Account for an extra tick period if a tick increment's pending. Close #2230.
* bsps/powerpc: Fix switch statement in CPU identSebastian Huber2015-01-231-0/+2
| | | | Close #2237.
* powerpc: Fix AltiVec VSCR save/restoreSebastian Huber2015-01-201-4/+6
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* libcpu/powerpc/mpc6xx/mmu/bat.c: Now compiles with gcc 5.xJoel Sherrill2015-01-131-12/+12
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* powerpc: AltiVec and FPU context supportSebastian Huber2015-01-137-12/+821
| | | | | | | | | | | Add AltiVec and FPU support to the Context_Control in case we use the e6500 multilib. Add PPC_MULTILIB_ALTIVEC and PPC_MULTILIB_FPU multilib defines. Add non-volatile AltiVec and FPU context to Context_Control. Add save/restore of non-volatile AltiVec and FPU to _CPU_Context_switch(). Add save/restore of volatile AltiVec and FPU context to the exception code. Adjust data cache optimizations for the new context and cache line size.
* bsps/powerpc: Use e500 exc categories for e6500Sebastian Huber2015-01-131-0/+1
| | | | This is not correct, but works for now.
* powerpc: Use PPC_HAS_FPUSebastian Huber2015-01-091-6/+6
| | | | Provide floating point context support only if PPC_HAS_FPU == 1.
* powerpc: Set PPC_DEFAULT_CACHE_LINE_SIZE for e6500Sebastian Huber2015-01-091-15/+11
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* powerpc: Use PPC_DEFAULT_CACHE_LINE_SIZESebastian Huber2015-01-091-8/+2
| | | | | Use it for the default PPC_CACHE_ALIGNMENT. Use it for PPC_STRUCTURE_ALIGNMENT.
* bsps/powerpc: ppc_exc_initialize_interrupt_stack()Sebastian Huber2015-01-092-11/+20
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* bsps/powerpc: Add TMR access macrosSebastian Huber2015-01-091-0/+28
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* bsps/powerpc: Add cache size functionsSebastian Huber2015-01-091-0/+46
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* bsps/powerpc: Delete C pre-processor warningSebastian Huber2015-01-091-2/+0
| | | | Do not warn about not implemented cache functions.
* bsps/powerpc: Support a cache alignment of 64Sebastian Huber2015-01-091-1/+8
| | | | Give the BSP the ability to define PPC_CACHE_ALIGNMENT.
* bsps/powerpc: Support e6500 indentificationSebastian Huber2015-01-092-0/+12
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* bsps/mpc83xx: Fix warningsSebastian Huber2015-01-091-4/+5
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* Use fixed-width C99 types for PowerPC in_be16() and co.Nick Withers2014-12-231-21/+22
| | | | | | Also use the const qualifier on the address pointer's target in in_*() Closes #2128
* bsp/mpc8xx: Fix warningsSebastian Huber2014-12-121-2/+0
| | | | close #2211
* bsp/mpc8xx: Fix warningsSebastian Huber2014-12-123-11/+2
| | | | close #2211