| Commit message (Collapse) | Author | Age | Files | Lines |
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level.
New function arm_cp15_cache_invalidate_level and arm_cp15_cache_clean_level
can be used to maintain single cache level (instruction or data).
Updates #2782
Updates #2783
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The change documents meaning of codes and opens
well defined way to use cache type format for cache
examination/debugging outside of arm-cp15.h file.
Updates #2782
Updates #2783
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architecture variants now.
Next cache operations should work on most of cores now
rtems_cache_flush_entire_data()
rtems_cache_invalidate_entire_data()
rtems_cache_invalidate_entire_instruction()
Instruction cache invalidate works on the first level for now only.
Data cacache operations are extended to ensure flush/invalidate
on all cache levels.
The CP15 arm_cp15_data_cache_clean_all_levels() function extended
to continue through unified levels too (ctype = 4).
Updates #2782
Updates #2783
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Disabling MMU requires complex cache flushing and invalidation
operations. There is almost no way how to do that right
on SMP system without stopping all other CPUs. On the other hand,
there is documented sequence of operations which should be used
according to ARM manual and it guarantees even distribution
of maintenance operations to other cores for last generation
of Cortex-A cores with multiprocessor extension.
This change could require addition of appropriate entry
to arm_cp15_start_mmu_config_table for some BSPs to ensure
that MMU table stays accessible after MMU is enabled
{
.begin = (uint32_t) bsp_translation_table_base,
.end = (uint32_t) bsp_translation_table_base + 0x4000,
.flags = ARMV7_MMU_DATA_READ_WRITE_CACHED
}
Updates #2782
Updates #2783
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The basic data and instruction rage functions should be compatible
for all ARMv4,5,6,7 functions. On the other hand, some functions
are not portable, for example arm_cp15_data_cache_test_and_clean()
and arm_cp15_data_cache_invalidate() for all versions and there
has to be specialized version for newer cores.
arm_cache_l1_properties_for_level uses CCSIDR which is not present
on older chips.
Actual version is only experimental, needs more changes
and problem has been found on RPi1 with dlopen so there seems
to be real problem.
Updates #2783
Updates #2782
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BSPs.
The original ARM architecture wide cache_.h is changed to dummy version
for targets not implementing/enablig cache at all.
The ARM targets equipped by cache should include
appropriate implementation.
Next options are available for now
c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h
basic ARM cache integrated on the CPU core directly
which requires only CP15 oparations
c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
support for case where ARM L2C-310 cache controller
is used. It is accessible as mmaped peripheral.
c/src/lib/libbsp/arm/shared/armv7m/include/cache_.h
Cortex-M specific cache support
Updates #2782
Updates #2783
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and maximal alignment.
There is need for unambiguous named and defined cache function
which should be called when code is updated, loaded
or is self-modifying.
There should be function to obtain maximal cache line length
as well. This function can and should be used for allocations
which can be used for data and or code and ensures that
there are no partial cache lines overlaps on start and
end of allocated region.
Updates #2782
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base access.
The main reason for inclusion of minimum hypervisor related defines
is that current ARM boards firmware and loaders (U-boot for example)
start loaded operating system kernel in HYP mode to allow it take
control of virtualization (Linux/KVM for example).
Updates #2783
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Updates #2782
Updates #2783
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Properly pass the stack aligned context to _CPU_Context_switch_altivec()
since _CPU_altivec_ctxt_off defined via ppc_context.
Update #2761.
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The window underflow trap handler used %i5 which destroyed the %o5 of
the calling context. Bug introduced by
0d3b5d47429effb350448d9e9123a67db722109f.
Go back to the pre 0d3b5d47429effb350448d9e9123a67db722109f behaviour
and use the two unused instructions in the trap vector to optimize a
bit.
Close #2651.
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Close #2502.
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Close #2470.
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Close #2373.
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Drop the <rtems/score/percpu.h> include since this file exposes a lot of
implementation details.
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Store the floating-point unit property in the thread control block
regardless of the CPU_HARDWARE_FP and CPU_SOFTWARE_FP settings. Make
sure the floating-point unit is only enabled for the corresponding
multilibs. This helps targets which have a volatile only floating point
context like SPARC for example.
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Update #2356.
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Update #2271.
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Get rid of _CPU_cache_invalidate_instruction_range declaration
as it doesn't make sense here.
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fix warning
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The sparc64 port had some incorrect copyright notices affixed to
source code files.
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PowerPC Book E: Account for an extra tick period if a tick increment's
pending.
Close #2230.
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Close #2237.
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Add AltiVec and FPU support to the Context_Control in case we use the
e6500 multilib.
Add PPC_MULTILIB_ALTIVEC and PPC_MULTILIB_FPU multilib defines. Add
non-volatile AltiVec and FPU context to Context_Control. Add save/restore of
non-volatile AltiVec and FPU to _CPU_Context_switch(). Add save/restore
of volatile AltiVec and FPU context to the exception code. Adjust data
cache optimizations for the new context and cache line size.
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This is not correct, but works for now.
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Provide floating point context support only if PPC_HAS_FPU == 1.
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Use it for the default PPC_CACHE_ALIGNMENT. Use it for
PPC_STRUCTURE_ALIGNMENT.
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Do not warn about not implemented cache functions.
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Give the BSP the ability to define PPC_CACHE_ALIGNMENT.
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Also use the const qualifier on the address pointer's target in in_*()
Closes #2128
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close #2211
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close #2211
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