| Commit message (Collapse) | Author | Age | Files | Lines |
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The window underflow trap handler used %i5 which destroyed the %o5 of
the calling context. Bug introduced by
0d3b5d47429effb350448d9e9123a67db722109f.
Go back to the pre 0d3b5d47429effb350448d9e9123a67db722109f behaviour
and use the two unused instructions in the trap vector to optimize a
bit.
Close #2651.
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* Coding style cleanups.
* Use OS reserved trap 0x89 for IRQ Disable
* Use OS reserved trap 0x8A for IRQ Enable
* Add to SPARC CPU supplement documentation
This will result in faster Disable/Enable code since the
system trap handler does not need to decode which function
the user wants. Besides the IRQ disable/enabled can now
be inline which avoids the caller to take into account that
o0-o7+g1-g4 registers are destroyed by trap handler.
It was also possible to reduce the interrupt trap handler by
five instructions due to this.
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Save five instructions on underflow handling.
By using an optimized trap entry we can move instructions from
the window underflow function into the trap entry vector. By
setting WIM=0 and using RESTORE it is possible to move the
new WIM register content from the trapped window into the
to-be-restored register window. It is then possible to avoid
the WIM write delay.
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By using a optimized trap entry we can move instructions from
the window overflow function into the trap entry vector. By
using the saved locals instead of g1 we don't need to save
that register temporarily. Also spead out non store instructions
inbetween stores to use the write buffer better.
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I see no need for waiting the 3 instruction delay for wim to be
written in this case, since the STD after does not depend on WIM
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Make sure also the size is cache aligned since otherwise we may have
some overlap with the next allocation block. A cache invalidate on this
area would be fatal.
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Guest systems in paravirtualization environments run usually in user
mode. Thus it is not possible to directly access the PSR and TBR
registers. Use functions instead of inline assembler to access these
registers if RTEMS_PARAVIRT is defined.
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The last optimization missed was incorrect in regards to
PSR write instruction delay must be 3 instructions.
New optimizations:
* align to 32-byte cache line.
* rearrange code into three "blocks" of 4 instructions that
is executed by syscall 2 and 3. This is to optimize for
16/32 byte cache lines.
* use delay-slot instruction in trap table to reduce by one
instruction.
* use the fact that "wr %PSR" implements XOR to reduce by
one instruction.
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The exit SPARC system call doesn't have a function entry
point like the others do. This is probably why people use
TA 0x0 instruction directly for shutting down the system.
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This commit deletes all RTEMS ChangeLog files. These files have been abandoned
since converting to git version control. The historical data may be recovered
by checking out any commit before this one. Most of the contents of these
ChangeLog files can also be found in the git log.
Two external ChangeLog files, ChangeLog.slac and ChangeLog.zlib, remain.
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Script does what is expected and tries to do it as
smartly as possible.
+ remove occurrences of two blank comment lines
next to each other after Id string line removed.
+ remove entire comment blocks which only exited to
contain CVS Ids
+ If the processing left a blank line at the top of
a file, it was removed.
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The low level routines can be used in different occasions, it will be
required when accessing PCI.
Note the difference between byteorder.h (inlined functions) and access.S
where the functions will be declared in the library archive librtemscpu.a.
Function names starting with _ are in library and can be referenced by
function pointers.
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
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* cache/cache.c:
Use "__asm__" instead of "asm" for improved c99-compliance.
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* configure.ac: Require autoconf-2.68, automake-1.11.1.
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* preinstall.am: Regenerated.
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* Makefile.am: Remove superfluous $(top_srcdir).
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PR 1249/build
* configure.ac: Jerry Needell <jerry.needell@unh.edu> reported that the
leon3 was left out of the cache enable logic. Thus the cache
management support code was empty on LEON3 CPUs.
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* configure.ac: New BUG-REPORT address.
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* configure.ac: Require autoconf-2.60. Require automake-1.10.
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* configure.ac: Use RTEMS_AMPOLISH3.
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* configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP.
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* preinstall.am: New.
* Makefile.am: Include preinstall.am.
* configure.ac: Reflect changes above.
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* Makefile.am: Eliminate CFLAGS_OPTIMIZE_V.
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* Makefile.am: Remove build-variant support.
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* configure.ac: Remove RTEMS_ENABLE_BARE.
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* configure.ac: Require automake > 1.9.
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* reg_win/window.S: Include <rtems/asm.h> instead of <asm.h>.
* syscall/syscall.S: Include <rtems/asm.h> instead of <asm.h>.
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* configure.ac: Add 2nd argument (rtems_updir) to RTEMS_TOP.
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