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The previous cache manager support used a single souce file
(cache_manager.c) which included an implementation header (cache_.h).
This required the use of specialized include paths to find the right
header file. Change this to include a generic implementation header
(cacheimpl.h) in specialized source files.
Use the following directories and files:
* bsps/shared/cache
* bsps/@RTEMS_CPU@/shared/cache
* bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILY/start/cache.c
Update #3285.
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and maximal alignment.
There is need for unambiguous named and defined cache function
which should be called when code is updated, loaded
or is self-modifying.
There should be function to obtain maximal cache line length
as well. This function can and should be used for allocations
which can be used for data and or code and ensures that
there are no partial cache lines overlaps on start and
end of allocated region.
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Add CPU_CACHE_LINE_BYTES for the maximum cache line size in bytes. The
actual processor may use no cache or a smaller cache line size.
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Adds functions that allows the user to specify which cores that should
perform the cache operation. SMP messages are sent to all the specified
cores and the caller waits until all cores have acknowledged that they
have flushed their cache. If CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING is
defined the instruction cache invalidation function will perform the
operation on all cores using the previous method.
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Add rtems_cache_get_data_cache_size() and
rtems_cache_get_instruction_cache_size().
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A cache line cannot have a negative size.
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According with comment in
rtems_cache_invalidate_multiple_instruction_lines(), final_address
indicates the last address which needs to be invalidated. But if in
while loop we got final_address == i_addr condition then loop breaks and
final_address will not be invalidated.
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* shared/include/cache.h, shared/src/cache_manager.c: Removed include
files to reduce implementation constraints.
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* shared/include/cache.h, shared/src/cache_aligned_malloc.c,
shared/src/cache_manager.c: URL for license changed.
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* shared/src/cache_manager.c
(rtems_cache_invalidate_multiple_instruction_lines): If
CPU_INSTRUCTION_CACHE_ALIGNMENT is defined but 0, then there is
an instruction cache but no notion of line size.
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* shared/src/cache_manager.c: Minor bug fix -- changed > to >= so the
last address is invalidated.
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* shared/src/cache_manager.c (rtems_cache_flush_multiple_data_lines,
rtems_cache_invalidate_multiple_data_lines): Do not operate on the
entire address space when flushing zero bytes.
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routine naming to follow RTEMS package/object.method rule.
This patch also eliminated calls to the obsolete routine
m68k_enable_caching.
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now is an implementation of the prototypes in rtems/rtems/cache.h.
The libcpu/i386/wrapup directory is no longer needed.
The PowerPC needs this done to it.
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<charles.gauthier@iit.nrc.ca>, and Darlene A. Stewart
<Darlene.Stewart@nrc.ca> to add support for a number of very
significant things:
+ BSPs for many variations on the Motorola MBX8xx board series
+ Cache Manager including initial support for m68040
and PowerPC
+ Rework of mpc8xx libcpu code so all mpc8xx CPUs now use
same code base.
+ Rework of eth_comm BSP to utiltize above.
John reports this works on the 821 and 860
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