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* score: Fix interrupt profilingSebastian Huber2016-11-241-20/+13
| | | | | | | | | | Callers of _Thread_Do_dispatch() must have a valid Per_CPU_Control::Stats::thread_dispatch_disabled_instant. Call _Profiling_Outer_most_interrupt_entry_and_exit() with the interrupt stack to not exceed Per_CPU_Control::Interrupt_frame. Update #2751.
* powerpc: Fix interrupt profiling for e6500Sebastian Huber2016-11-241-1/+3
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* powerpc/mpc5xx: Rename CPU_Interrupt_frameSebastian Huber2016-11-212-4/+4
| | | | | | The MPC5XX support uses a legacy interrupt/exception infrastructure. Close #2819.
* powerpc: Use Per_CPU_Control::isr_dispatch_disableSebastian Huber2016-11-182-20/+66
| | | | Update #2751.
* score: Allow interrupts during thread dispatchSebastian Huber2016-11-181-12/+17
| | | | | | | | | Use a processor-specific interrupt frame during context switches in case the executing thread is longer executes on the processor and the heir thread is about to start execution. During this period we must not use a thread stack for interrupt processing. Update #2809.
* powerpc: Add up to date CPU_Interrupt_frameSebastian Huber2016-11-183-379/+4
| | | | | | | Rename ppc_exc_min_frame to CPU_Interrupt_frame. Move it and the corresponding defines to <rtems/score/cpuimpl.h>. Update #2809.
* powerpc: Move legacy CPU_Interrupt_frameSebastian Huber2016-11-181-0/+33
| | | | | | | The only remaining user of CPU_Interrupt_frame on PowerPC is the mpc5xx support. Move it to here. Update #2809.
* bsps/powerpc: Avoid use of CPU_Interrupt_frameSebastian Huber2016-11-181-3/+3
| | | | | | | This type is not relevant for the code since only a pointer is passed around. Update #2809.
* powerpc: Add _CPU_Get_current_per_CPU_control()Sebastian Huber2016-11-101-1/+8
| | | | | | | | Add _CPU_Get_current_per_CPU_control() on SMP configurations. Use SPRG0 for the current per-CPU control. This reduces the code size by three instructions and is slightly faster. Update #2805.
* score: Add and use Thread_Control::is_idleSebastian Huber2016-11-091-5/+1
| | | | Update #2797.
* powerpc: Fix SMP context switchSebastian Huber2016-09-081-61/+62
| | | | | | We need the unmodified r4 for get_potential_new_heir. This partially reverts commit 8d785f72d9610fb80a65d7848404f0f7507e026c.
* bsps/powerpc: Fix AtliVec context switchSebastian Huber2016-07-192-62/+68
| | | | | | | Properly pass the stack aligned context to _CPU_Context_switch_altivec() since _CPU_altivec_ctxt_off defined via ppc_context. Close #2761.
* score: Rename _ISR_Disable() and _ISR_Enable()Sebastian Huber2016-05-202-4/+4
| | | | | | | | | Rename _ISR_Disable() into _ISR_Local_disable(). Rename _ISR_Enable() into _ISR_Local_enable(). Remove _Debug_Is_owner_of_giant(). This is a preparation to remove the Giant lock. Update #2555.
* score: Rename _ISR_Disable_without_giant()Sebastian Huber2016-05-201-12/+12
| | | | | | | | | Rename _ISR_Disable_without_giant() into _ISR_Local_disable(). Rename _ISR_Enable_without_giant() into _ISR_Local_enable(). This is a preparation to remove the Giant lock. Update #2555.
* Delete unused API extensionsSebastian Huber2016-02-033-3/+0
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* score: Introduce Thread_Entry_informationSebastian Huber2016-01-111-2/+2
| | | | | | | This avoids potential dead code in _Thread_Handler(). It gets rid of the dangerous function pointer casts. Update #2514.
* Fix interrupt epilogue for ARMv7-AR and PowerPCSebastian Huber2015-11-121-13/+38
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* SMP: Fix and optimize thread dispatchingSebastian Huber2015-09-282-15/+19
| | | | | | | | According to the C11 and C++11 memory models only a read-modify-write operation guarantees that we read the last value written in modification order. Avoid the sequential consistent thread fence and instead use the inter-processor interrupt to set the thread dispatch necessary indicator.
* bsp/mpc83xx: Update due to header guard changeSebastian Huber2015-07-172-6/+6
| | | | Close #2373.
* bsps/powerpc: Provide debug and trace symbolsSebastian Huber2015-07-081-0/+3
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* score: Simplify <rtems/system.h>Sebastian Huber2015-06-262-0/+2
| | | | | Drop the <rtems/score/percpu.h> include since this file exposes a lot of implementation details.
* score: Add Thread_Control::is_fpSebastian Huber2015-06-091-17/+1
| | | | | | | | Store the floating-point unit property in the thread control block regardless of the CPU_HARDWARE_FP and CPU_SOFTWARE_FP settings. Make sure the floating-point unit is only enabled for the corresponding multilibs. This helps targets which have a volatile only floating point context like SPARC for example.
* bsps/powerpc: Fix potential integer overflowSebastian Huber2015-05-291-1/+1
| | | | Update #2356.
* bsps: Convert clock drivers to use a timecounterAlexander Krutwig2015-05-201-78/+29
| | | | Update #2271.
* libcpu/powerpc/mpc8260/console-generic/console-generic.c: Include bsp.h to ↵Joel Sherrill2015-03-091-3/+1
| | | | fix warning
* bsps/powerpc: Fix a clock driverNick Withers2015-01-301-9/+57
| | | | | | | PowerPC Book E: Account for an extra tick period if a tick increment's pending. Close #2230.
* bsps/powerpc: Fix switch statement in CPU identSebastian Huber2015-01-231-0/+2
| | | | Close #2237.
* powerpc: Fix AltiVec VSCR save/restoreSebastian Huber2015-01-201-4/+6
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* libcpu/powerpc/mpc6xx/mmu/bat.c: Now compiles with gcc 5.xJoel Sherrill2015-01-131-12/+12
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* powerpc: AltiVec and FPU context supportSebastian Huber2015-01-137-12/+821
| | | | | | | | | | | Add AltiVec and FPU support to the Context_Control in case we use the e6500 multilib. Add PPC_MULTILIB_ALTIVEC and PPC_MULTILIB_FPU multilib defines. Add non-volatile AltiVec and FPU context to Context_Control. Add save/restore of non-volatile AltiVec and FPU to _CPU_Context_switch(). Add save/restore of volatile AltiVec and FPU context to the exception code. Adjust data cache optimizations for the new context and cache line size.
* bsps/powerpc: Use e500 exc categories for e6500Sebastian Huber2015-01-131-0/+1
| | | | This is not correct, but works for now.
* powerpc: Use PPC_HAS_FPUSebastian Huber2015-01-091-6/+6
| | | | Provide floating point context support only if PPC_HAS_FPU == 1.
* powerpc: Set PPC_DEFAULT_CACHE_LINE_SIZE for e6500Sebastian Huber2015-01-091-15/+11
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* powerpc: Use PPC_DEFAULT_CACHE_LINE_SIZESebastian Huber2015-01-091-8/+2
| | | | | Use it for the default PPC_CACHE_ALIGNMENT. Use it for PPC_STRUCTURE_ALIGNMENT.
* bsps/powerpc: ppc_exc_initialize_interrupt_stack()Sebastian Huber2015-01-092-11/+20
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* bsps/powerpc: Add TMR access macrosSebastian Huber2015-01-091-0/+28
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* bsps/powerpc: Add cache size functionsSebastian Huber2015-01-091-0/+46
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* bsps/powerpc: Delete C pre-processor warningSebastian Huber2015-01-091-2/+0
| | | | Do not warn about not implemented cache functions.
* bsps/powerpc: Support a cache alignment of 64Sebastian Huber2015-01-091-1/+8
| | | | Give the BSP the ability to define PPC_CACHE_ALIGNMENT.
* bsps/powerpc: Support e6500 indentificationSebastian Huber2015-01-092-0/+12
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* bsps/mpc83xx: Fix warningsSebastian Huber2015-01-091-4/+5
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* Use fixed-width C99 types for PowerPC in_be16() and co.Nick Withers2014-12-231-21/+22
| | | | | | Also use the const qualifier on the address pointer's target in in_*() Closes #2128
* bsp/mpc8xx: Fix warningsSebastian Huber2014-12-121-2/+0
| | | | close #2211
* bsp/mpc8xx: Fix warningsSebastian Huber2014-12-123-11/+2
| | | | close #2211
* Update bug report URLSebastian Huber2014-12-051-1/+1
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* rtems: Move rtems_cache_aligned_malloc()Sebastian Huber2014-11-251-1/+1
| | | | | | Make sure also the size is cache aligned since otherwise we may have some overlap with the next allocation block. A cache invalidate on this area would be fatal.
* powerpc/haleakala: Add network driverNigel Spon2014-11-212-40/+143
| | | | close 1405
* bsp/mpc55xxevb: Fix flash settings for MPC5510Sebastian Huber2014-10-311-1/+2
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* libcpu/powerpc configure logic: Do not built e500 components unused by qoriqJoel Sherrill2014-10-193-6/+17
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* libcpu/powerpc/ppc403/console/console405.c: Fix warningsJoel Sherrill2014-10-161-18/+6
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