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* 2011-01-31 Sebastian Huber <sebastian.huber@embedded-brains.de>Sebastian Huber2011-01-311-4/+20
| | | | | | | | | * new-exceptions/bspsupport/ppc_exc.S, new-exceptions/bspsupport/ppc_exc_asm_macros.h, new-exceptions/bspsupport/ppc_exc_naked.S, new-exceptions/bspsupport/ppc_exc_prologue.c: Branch targets are now global for all minimal prologues. Generate branch instruction in minimal prologues.
* 2010-12-29 Sebastian Huber <sebastian.huber@embedded-brains.de>Sebastian Huber2010-12-291-26/+0
| | | | | | | | | | | | | | | | * shared/include/cpuIdent.c, shared/include/cpuIdent.h: Added support for e500v2. Removed IVPR/IVOR/HWIVOR features since they are included in Book E. * new-exceptions/bspsupport/vectors.h, new-exceptions/bspsupport/ppc_exc.S, new-exceptions/bspsupport/ppc_exc_address.c, new-exceptions/bspsupport/ppc_exc_categories.c, new-exceptions/bspsupport/ppc_exc_initialize.c, new-exceptions/bspsupport/ppc_exc_prologue.c: Added support for e500v2. Added exception vector defines for Book E types. Removed e200 exception vector defines. Added e500 exception vector defines. Unified IVOR calculation for e200 and e500 (e200z1 has hard wired IVOR values).
* 2010-12-22 Sebastian Huber <sebastian.huber@embedded-brains.de>Sebastian Huber2010-12-221-0/+6
| | | | | | * new-exceptions/bspsupport/ppc_exc.S: Comment. * new-exceptions/bspsupport/ppc_exc_address.c: Fixed address calculation for e200z1 core.
* 2010-06-28 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill2010-06-291-0/+4
| | | | | | | | | | | PR 1573/cpukit * mpc5xx/irq/irq.c, mpc5xx/irq/irq_asm.S, new-exceptions/bspsupport/ppc_exc.S, new-exceptions/bspsupport/ppc_exc_asm_macros.h, new-exceptions/bspsupport/ppc_exc_hdl.c: Add a per cpu data structure which contains the information required by RTEMS for each CPU core. This encapsulates information such as thread executing, heir, idle and dispatch needed.
* Update for exception support changes.Thomas Doerfler2009-10-231-3/+3
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* adapted powerpc exception codeThomas Doerfler2008-07-111-289/+72
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* 2008-07-10 Till Straumann <strauman@slac.stanford.edu>Till Straumann2008-07-101-0/+20
| | | | | * new-exceptions/bspsupport/ppc_exc.S: must disable interrupts prior to restoring SRRs (thanks to Sebastian Huber)
* 2008-03-13 Till Straumann <strauman@slac.stanford.edu>Till Straumann2008-03-131-6/+12
| | | | | | | | | | | | | | | * new-exceptions/bspsupport/ppc_exc_asm_macros.h, new-exceptions/bspsupport/ppc_exc.S, new-exceptions/bspsupport/README, new-exceptions/bspsupport/ppc_exc_hdl.c: Thomas Doerfler clarified (thanks!) that raising an exception and executing the 1st instruction is not an atomical operation. I added a fix to the code that checks if a lower-priority interrupt is under way: we now not only test if the 'lock' variable was set but also check if the interrupted PC points to the 'write lock' instruction. Added more comments and updated README.
* 2007-12-08 Till Straumann <strauman@slac.stanford.edu>Till Straumann2007-12-081-0/+368
* new-exceptions/bspsupport/, new-exceptions/bspsupport/ppc_exc.S, new-exceptions/bspsupport/ppc_exc_test.c, new-exceptions/bspsupport/vectors.h, new-exceptions/bspsupport/vectors_init.c, new-exceptions/bspsupport/irq.c, new-exceptions/bspsupport/ppc_exc_bspsupp.h, new-exceptions/bspsupport/ppc_exc_hdl.c, new-exceptions/bspsupport/ppc_exc_asm_macros.h, new-exceptions/bspsupport/nested_irq_test.c: New files. Added 'middleware' code for helping BSPs implement exception and interrupt handling and implementing the 'new' RTEMS IRQ API (which I personally dislike).