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2007-12-012007-11-29 Till Straumann <strauman@slac.stanford.edu>Till Straumann1-350/+0
* mpc6xx/exceptions/raw_exception.c, mpc6xx/exceptions/raw_exception.h: removed. mpc6xx uses generic version in new-exceptions.
2007-09-122007-09-12 Joel Sherrill <joel.sherrill@OARcorp.com>Joel Sherrill1-10/+10
PR 1257/bsps * mpc5xx/exceptions/raw_exception.c, mpc5xx/irq/irq.c, mpc6xx/exceptions/raw_exception.c, mpc8260/exceptions/raw_exception.c, mpc8xx/exceptions/raw_exception.c, new-exceptions/raw_exception.c, ppc403/ictrl/ictrl.c, ppc403/irq/ictrl.c: Code outside of cpukit should use the public API for rtems_interrupt_disable/rtems_interrupt_enable. By bypassing the public API and directly accessing _CPU_ISR_Disable and _CPU_ISR_Enable, they were bypassing the compiler memory barrier directive which could lead to problems. This patch also changes the type of the variable passed into these routines and addresses minor style issues.
2006-06-19 Added altivec exception. Unfortunately, this doesn't fitTill Straumann1-4/+27
the normal scheme of vector = exception # << 8. So we picked an unused vector number (currently 0xa) where we map the special vector 0xf20 (altivec).
2005-12-312005-12-31 Ralf Corsepius <ralf.corsepius@rtems.org>Ralf Corsepius1-0/+1
PR 851/bsps * mpc6xx/exceptions/raw_exception.c: Add PPC_603le.
2005-12-31Cosmetics.Ralf Corsepius1-9/+9
2005-11-022005-11-02 straumanatslacdotstanford.eduTill Straumann1-0/+1
* ChangeLog, configure.ac, mpc6xx/exceptions/raw_exception.c, shared/include/cpuIdent.c, shared/include/cpuIdent.h: recognize mpc7457 CPU; added definitions for high bats (#4..7) on 7450 CPUs
2004-11-222004-11-22 Jennifer Averett <jennifer@OARcorp.com>Jennifer Averett1-0/+36
PR 581/bsps * mpc6xx/exceptions/raw_exception.c, shared/include/cpuIdent.h: Converting PSIM to new exception model required adding PSIM as PowerPC CPU model.
2004-11-102004-11-10 Richard Campbell <richard.campbell@oarcorp.com>Joel Sherrill1-6/+27
* configure.ac, mpc6xx/exceptions/raw_exception.c, mpc6xx/exceptions/raw_exception.h, mpc6xx/mmu/bat.c, mpc6xx/mmu/bat.h, mpc6xx/mmu/mmuAsm.S, shared/include/cpuIdent.c, shared/include/cpuIdent.h: Add MPC8240 and MPC8245 support. There was also a significant amount of spelling and whitespace cleanup.
2004-10-20Add Kate Feng's MVME5500 BSP.Eric Norum1-0/+1
2004-04-15Remove stray white spaces.Ralf Corsepius1-1/+0
2004-04-132004-04-13 Ralf Corsepius <ralf_corsepius@rtems.org>Ralf Corsepius1-1/+1
* mpc505/ictrl/ictrl.c, mpc505/vectors/vectors.S, mpc6xx/exceptions/raw_exception.c, mpc8260/exceptions/raw_exception.c, mpc8xx/exceptions/raw_exception.c, rtems/powerpc/cache.h, mpc5xx/ictrl/ictrl.c, mpc5xx/exceptions/raw_exception.c: Include <rtems/score/powerpc.h> instead of <rtems/score/ppc.h>.
2003-09-042003-09-04 Joel Sherrill <joel@OARcorp.com>Joel Sherrill1-1/+1
* mpc6xx/clock/c_clock.c, mpc6xx/clock/c_clock.h, mpc6xx/exceptions/raw_exception.c, mpc6xx/exceptions/raw_exception.h, mpc6xx/mmu/bat.c, mpc6xx/mmu/bat.h, mpc6xx/mmu/mmuAsm.S, mpc6xx/timer/timer.c, mpc8260/clock/clock.c, mpc8260/console-generic/console-generic.c, mpc8260/cpm/brg.c, mpc8260/exceptions/raw_exception.c, mpc8260/exceptions/raw_exception.h, mpc8260/include/cpm.h, mpc8260/include/mmu.h, mpc8260/mmu/mmu.c, mpc8260/timer/timer.c, mpc8xx/clock/clock.c, mpc8xx/console-generic/console-generic.c, mpc8xx/exceptions/raw_exception.c, mpc8xx/exceptions/raw_exception.h, mpc8xx/include/cpm.h, mpc8xx/include/mmu.h, mpc8xx/mmu/mmu.c, mpc8xx/timer/timer.c, ppc403/clock/clock.c, ppc403/console/console.c.polled, ppc403/timer/timer.c, rtems/powerpc/debugmod.h, shared/include/byteorder.h, shared/include/cpuIdent.c, shared/include/cpuIdent.h, shared/include/io.h, shared/include/mmu.h, shared/include/page.h, shared/include/pgtable.h, shared/include/spr.h: URL for license changed.
2003-02-202003-02-20 Till Straumann <strauman@slac.stanford.edu>Joel Sherrill1-2/+2
PR 349/bsps * mpc6xx/exceptions/raw_exception.c, mpc6xx/mmu/bat.c, mpc6xx/mmu/pte121.c, shared/include/cpuIdent.c, shared/include/cpuIdent.h, shared/src/Makefile.am, shared/src/stack.c, shared/src/stackTrace.h, powerpc/registers.h: - undo improper 'fix' who broke mpc604r identification - fix: 7400 identification PVR value was wrong - enhance 'setdbat()' to switch OFF a given BAT if called with 0 size - fix: page table support bugfix - enhancement: provide routines to take and print stack trace snapshots - add definitions for HID1 and DABR SPRs
2003-02-142003-02-14 Greg Menke <gregory.menke@gsfc.nasa.gov>Joel Sherrill1-0/+1
PR 348/bsps * mpc6xx/exceptions/raw_exception.c: Add PPC_603ev as required by MTX603e BSP.
2002-10-312002-10-31 Joel Sherrill <joel@OARcorp.com>Joel Sherrill1-0/+4
* mpc6xx/clock/c_clock.c, mpc6xx/exceptions/raw_exception.c, mpc6xx/mmu/bat.c: Removed warnings.
2002-05-172001-05-17 Joel Sherrill <joel@OARcorp.com>Joel Sherrill1-2/+2
* mpc6xx/exceptions/raw_exception.c, pc6xx/mmu/pte121.c: Modified slightly to reflect recent PowerPC re-organization and avoid warnings.
2002-05-142001-05-14 Till Straumann <strauman@slac.stanford.edu>Joel Sherrill1-0/+1
* rtems/powerpc/registers.h, rtems/score/ppc.h: Per PR213, add the following: - support for the MPC74000 (AKA G4); there is no AltiVec support yet, however. - the cache flushing assembly code uses hardware-flush on the G4. Also, a couple of hardcoded numerical values were replaced by more readable symbolic constants. - extended interrupt-disabled code section so enclose the entire cache flush/invalidate procedure (as recommended by the book). This is not (latency) critical as it is only used by init code but prevents possible corruption. - Trivial page table support as been added. (1:1 effective-virtual-physical address mapping which is only useful only on CPUs which feature hardware TLB replacement, e.g. >604. This allows for write-protecting memory regions, e.g. text/ro-data which makes catching corruptors a lot easier. It also frees one DBAT/IBAT and gives more flexibility for setting up address maps :-) - setdbat() allows changing BAT0 also (since the BSP may use a page table, BAT0 could be available...). - asm_setdbatX() violated the SVR ABI by using r20 as a scratch register; changed for r0 - according to the book, a context synchronizing instruction is necessary prior to and after changing a DBAT -> isync added
2002-04-182002-04-18 Ralf Corsepius <corsepiu@faw.uni-ulm.de>Joel Sherrill1-3/+1
* shared/include/cpu.h: Removed. * shared/include/Makefile.am: Reflect changes above. * shared/include/spr.h: Include rtems/powerpc/registers.h instead of libcpu/cpu.h. * mpc6xx/clock/c_clock.c: Reflect changes to <rtems/score/cpu.h>. * mpc6xx/exceptions/asm_utils.S: Ditto. * mpc6xx/exceptions/raw_exception.c: Ditto. * mpc6xx/mmu/mmuAsm.S: Ditto. * mpc6xx/timer/timer.c: Ditto. * mpc8260/exceptions/asm_utils.S: Ditto. * mpc8260/exceptions/raw_exception.c: Ditto. * mpc8xx/exceptions/asm_utils.S: Ditto. * mpc8xx/exceptions/raw_exception.c: Ditto. * ppc403/vectors/vectors.S: Include <asm.h> instead of "asm.h".
2002-04-172002-04-16 Ralf Corsepius <corsepiu@faw.uni-ulm.de>Joel Sherrill1-0/+1
* exceptions/raw_exception.c: Include <libcpu/cpuIdent.h>.
2000-07-06Patch from Eric Valette <valette@crf.canon.fr>Joel Sherrill1-11/+18
2000-01-03Combination of coverhd.h cleanup and MVME23xx/MCP750 patch from Eric ValetteJoel Sherrill1-19/+80
<valette@crf.canon.fr> and Jay Kulpinski <jskulpin@eng01.gdds.com>.
1999-12-02Merged of mcp750 and mvme2307 BSP by Eric Valette <valette@crf.canon.fr>.Joel Sherrill1-0/+195
As part of this effort, the mpc750 libcpu code is now shared with the ppc6xx.
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