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* bsps/arm: reorganize CP15 code to allow clean and invalidate ARMv7 cache by ↵Pavel Pisa2016-10-021-48/+60
| | | | | | | | | | level. New function arm_cp15_cache_invalidate_level and arm_cp15_cache_clean_level can be used to maintain single cache level (instruction or data). Updates #2782 Updates #2783
* bsps/arm: use defines for cache type register format field.Pavel Pisa2016-10-021-9/+30
| | | | | | | | | The change documents meaning of codes and opens well defined way to use cache type format for cache examination/debugging outside of arm-cp15.h file. Updates #2782 Updates #2783
* arm/bsps: CP15 and basic cache support entire cache clean for more ↵Pavel Pisa2016-10-021-2/+42
| | | | | | | | | | | | | | | | | | | | architecture variants now. Next cache operations should work on most of cores now rtems_cache_flush_entire_data() rtems_cache_invalidate_entire_data() rtems_cache_invalidate_entire_instruction() Instruction cache invalidate works on the first level for now only. Data cacache operations are extended to ensure flush/invalidate on all cache levels. The CP15 arm_cp15_data_cache_clean_all_levels() function extended to continue through unified levels too (ctype = 4). Updates #2782 Updates #2783
* bsps/arm: do not disable MMU during translation table management operations.Pavel Pisa2016-10-021-0/+16
| | | | | | | | | | | | | | | | | | | | | | | Disabling MMU requires complex cache flushing and invalidation operations. There is almost no way how to do that right on SMP system without stopping all other CPUs. On the other hand, there is documented sequence of operations which should be used according to ARM manual and it guarantees even distribution of maintenance operations to other cores for last generation of Cortex-A cores with multiprocessor extension. This change could require addition of appropriate entry to arm_cp15_start_mmu_config_table for some BSPs to ensure that MMU table stays accessible after MMU is enabled { .begin = (uint32_t) bsp_translation_table_base, .end = (uint32_t) bsp_translation_table_base + 0x4000, .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED } Updates #2782 Updates #2783
* bsps/arm: basic on core cache support changed to use l1 functions.Pavel Pisa2016-10-021-3/+28
| | | | | | | | | | | | | | | | | The basic data and instruction rage functions should be compatible for all ARMv4,5,6,7 functions. On the other hand, some functions are not portable, for example arm_cp15_data_cache_test_and_clean() and arm_cp15_data_cache_invalidate() for all versions and there has to be specialized version for newer cores. arm_cache_l1_properties_for_level uses CCSIDR which is not present on older chips. Actual version is only experimental, needs more changes and problem has been found on RPi1 with dlopen so there seems to be real problem. Updates #2783 Updates #2782
* bsps/arm: Change code to explicit selection of cache implementation for ARM ↵Pavel Pisa2016-10-021-104/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | BSPs. The original ARM architecture wide cache_.h is changed to dummy version for targets not implementing/enablig cache at all. The ARM targets equipped by cache should include appropriate implementation. Next options are available for now c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h basic ARM cache integrated on the CPU core directly which requires only CP15 oparations c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h support for case where ARM L2C-310 cache controller is used. It is accessible as mmaped peripheral. c/src/lib/libbsp/arm/shared/armv7m/include/cache_.h Cortex-M specific cache support Updates #2782 Updates #2783
* arm/score and shared: define ARM hypervisor mode and alternate vector table ↵Pavel Pisa2016-10-021-0/+30
| | | | | | | | | | | base access. The main reason for inclusion of minimum hypervisor related defines is that current ARM boards firmware and loaders (U-boot for example) start loaded operating system kernel in HYP mode to allow it take control of virtualization (Linux/KVM for example). Updates #2783
* bsps/arm: CP15 support for flush prefetch buffer and table base control.Pavel Pisa2016-10-021-0/+48
| | | | | Updates #2782 Updates #2783
* score: Fix simple timecounter supportSebastian Huber2016-01-271-14/+18
| | | | Close #2502.
* beagle bsp: RTC support for BBBragunath2015-05-282-0/+26
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* arm/s3c24xx/clock/clockdrv.c: Remove unused variable warningJoel Sherrill2015-05-211-1/+0
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* arm/lpc22xx/clock/clockdrv.c: Remove unused variable warningJoel Sherrill2015-05-211-1/+0
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* bsps: Convert clock drivers to use a timecounterAlexander Krutwig2015-05-205-44/+51
| | | | Update #2271.
* Replace www.rtems.com with www.rtems.orgSebastian Huber2015-03-202-2/+2
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* Update bug report URLSebastian Huber2014-12-051-1/+1
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* beagle bsp: disable watchdog on am335xBen Gras2014-12-051-0/+6
| | | | | | | | | | | | On recent u-boots, the watchdog is turned on / left enabled. The Beaglebone Black rev. C ships with such a u-boot internally so any application booting from it must disable the watchdog. Therefore this change is needed to boot an RTEMS app out-of-the-box on a BBB Rev C - otherwise the user button must be held during boot (to bypass the stock uboot) or the internal uboot must be updated. To allow for a better out-of-the-box experience, we just turn off the watchdog.
* Add some generic ARM am335x and omap definitionsBen Gras2014-11-033-0/+692
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* libcpu/arm/pxa255/ffuart/ffuart.c: Fix warningJoel Sherrill2014-10-201-1/+1
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* libcpu/arm/at91rm9200/dbgu/dbgu.c: Fix warningJoel Sherrill2014-10-201-2/+2
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* libcpu/arm/at91rm9200/usart/usart.c: Fix warningsJoel Sherrill2014-10-161-15/+3
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* Remove unused pxa255/pmc, update csb337 and gumstix BSPsJoel Sherrill2014-10-162-132/+0
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* libcpu/arm/shared/../mmu: Fix warningsJoel Sherrill2014-10-162-4/+11
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* libcpu/arm/s3c24xx/clock/clockdrv.c: Fix warningsJoel Sherrill2014-10-131-5/+5
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* libcpu/arm/pxa255/clock/clock.c: Fix warningsJoel Sherrill2014-10-131-18/+11
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* libcpu/arm/mc9328mxl/clock/clockdrv.c: Fix warningsJoel Sherrill2014-10-131-10/+10
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* libcpu/arm/lpc22xx/clock/clockdrv.c: Fix warningsJoel Sherrill2014-10-131-5/+6
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* libcpu/arm/at91rm9200/clock/clock.c: Fix warningsJoel Sherrill2014-10-131-4/+8
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* Use correct prototype of benchmark_timer_read()Joel Sherrill2014-09-165-80/+58
| | | | | | | | | | | | | | This change starts with removing the effectively empty file timerdrv.h. The prototypes for benchmark_timer_XXX() were in btimer.h which was not universally used. Thus every use of timerdrv.h had to be changed to btimer.h. Then the prototypes for benchmark_timer_read() had to be adjusted to return benchmark_timer_t rather than int or uint32_t. I took this opportunity to also correct the file headers to separate the copyright from the file description comments which is needed to ensure the copyright isn't propagated into Doxygen output.
* Regenerate all preinstall.am files.Chris Johns2014-08-291-3/+3
| | | | | With this patch the preinstall.am files are in a set order and not dependent on now perl implements a hash.
* Regenerate all preinstall.am files.Joel Sherrill2014-08-281-3/+3
| | | | | Apparently, at some point automake output changed and these were not updated.
* bsps/arm: Fix TLB invalidation for ARMv7-ASebastian Huber2014-06-061-0/+7
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* bsps/arm: Add ARM_CP15_TEXT_SECTIONSebastian Huber2014-06-051-63/+134
| | | | | Allow users of this header file to optionally place the inline functions into a non-standard section.
* bsps/arm: Add all level data cache invalidationSebastian Huber2014-06-051-2/+63
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* bsps/arm: TypoSebastian Huber2014-06-051-1/+1
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* Change all references of rtems.com to rtems.org.Chris Johns2014-03-2142-42/+42
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* bsp/arm: Add CP15 methodsRalf Kirchner2014-03-131-1/+98
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* bsps/arm: Use Normal memory for code and dataSebastian Huber2014-01-131-3/+7
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* bsps/arm: ARMV7_MMU_DATA_READ_WRITE_SHAREABLESebastian Huber2013-10-271-5/+9
| | | | | Delete ARMV7_MMU_DATA_READ_WRITE_SHAREABLE and move RTEMS_SMP specific MMU attribute settings to arm-cp15.h.
* Add a new necessary definition needed for raspberrypi MMU supportHesham AL-Matary2013-10-031-0/+21
| | | | | | | | | | | The new ARM_CP15_CTRL_XP is necessary to share ARMv6 and ARMv7 page-table formats and definitions. It enables the extended page tables (introduced in ARMv6) to be configured for the hardware page translation mechanism. This way we can share ARMv6 and ARMv7 page tables entry formats. Other Fault Status Register Definitions can be useful for debugging or excpetion handlers.
* bsps/arm: Fix ARM CP15 opcode for get functionsSebastian Huber2013-09-051-3/+3
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* bsps/arm: Add more CP15 cache functionsRic Claus2013-08-221-0/+65
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* bsps: Fix clock driver definesSebastian Huber2013-08-141-1/+1
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* bsp/csb336: implement bsp_interrupt_vector_enable/disable.Pavel Pisa2013-08-091-0/+10
| | | | Signed-off-by: Pavel Pisa <ppisa@pikron.com>
* bsp/csb336: mc9328mxl correct AITC access in bsp_interrupt_dispatch.Pavel Pisa2013-07-261-1/+2
| | | | | | | | | | | The original version is missing void and result is that (*x >> 16) is optimized to ldh rX,[rY]. But it is not allowed/supported to access bus/address range used by AITC by other than 32 bit wide accesses and 16-bit access results in the data abort exception. The corrected version works on real hardware and is even more readable. Signed-off-by: Pavel Pisa <ppisa@pikron.com>
* bsps/arm: Set vector base address if necessarySebastian Huber2013-06-201-0/+47
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* bsps/arm: Add SMP supportSebastian Huber2013-05-311-0/+57
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* bsps/arm: Use Write-Allocate cache for ARMv7Sebastian Huber2013-05-311-2/+2
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* bsps/arm: Merge ARMv7 MMU section definitionsSebastian Huber2013-05-311-0/+43
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* bsps/arm: Remove superfluous parameterSebastian Huber2013-05-061-2/+1
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* bsps/arm: Support ARMv7 VMSA sections and controlSebastian Huber2013-05-031-4/+29
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