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level.
New function arm_cp15_cache_invalidate_level and arm_cp15_cache_clean_level
can be used to maintain single cache level (instruction or data).
Updates #2782
Updates #2783
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The change documents meaning of codes and opens
well defined way to use cache type format for cache
examination/debugging outside of arm-cp15.h file.
Updates #2782
Updates #2783
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architecture variants now.
Next cache operations should work on most of cores now
rtems_cache_flush_entire_data()
rtems_cache_invalidate_entire_data()
rtems_cache_invalidate_entire_instruction()
Instruction cache invalidate works on the first level for now only.
Data cacache operations are extended to ensure flush/invalidate
on all cache levels.
The CP15 arm_cp15_data_cache_clean_all_levels() function extended
to continue through unified levels too (ctype = 4).
Updates #2782
Updates #2783
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Disabling MMU requires complex cache flushing and invalidation
operations. There is almost no way how to do that right
on SMP system without stopping all other CPUs. On the other hand,
there is documented sequence of operations which should be used
according to ARM manual and it guarantees even distribution
of maintenance operations to other cores for last generation
of Cortex-A cores with multiprocessor extension.
This change could require addition of appropriate entry
to arm_cp15_start_mmu_config_table for some BSPs to ensure
that MMU table stays accessible after MMU is enabled
{
.begin = (uint32_t) bsp_translation_table_base,
.end = (uint32_t) bsp_translation_table_base + 0x4000,
.flags = ARMV7_MMU_DATA_READ_WRITE_CACHED
}
Updates #2782
Updates #2783
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The basic data and instruction rage functions should be compatible
for all ARMv4,5,6,7 functions. On the other hand, some functions
are not portable, for example arm_cp15_data_cache_test_and_clean()
and arm_cp15_data_cache_invalidate() for all versions and there
has to be specialized version for newer cores.
arm_cache_l1_properties_for_level uses CCSIDR which is not present
on older chips.
Actual version is only experimental, needs more changes
and problem has been found on RPi1 with dlopen so there seems
to be real problem.
Updates #2783
Updates #2782
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base access.
The main reason for inclusion of minimum hypervisor related defines
is that current ARM boards firmware and loaders (U-boot for example)
start loaded operating system kernel in HYP mode to allow it take
control of virtualization (Linux/KVM for example).
Updates #2783
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Updates #2782
Updates #2783
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Allow users of this header file to optionally place the inline functions
into a non-standard section.
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Delete ARMV7_MMU_DATA_READ_WRITE_SHAREABLE and move RTEMS_SMP
specific MMU attribute settings to arm-cp15.h.
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The new ARM_CP15_CTRL_XP is necessary to share ARMv6 and ARMv7
page-table formats and definitions.
It enables the extended page tables (introduced in ARMv6)
to be configured for the hardware page translation mechanism. This way
we can share ARMv6 and ARMv7 page tables entry formats.
Other Fault Status Register Definitions can be useful for debugging or
excpetion handlers.
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* pxa255/pmc/pmc.c, shared/include/arm-cp15.h:
Use "__asm__" instead of "asm" for improved c99-compliance.
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