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* Shared MMU initialization for ARM BSPs and RaspberryPi MMU supportHesham AL-Matary2013-10-038-31/+156
| | | | | | | Add support for MMU initialization for RaspberryPi. Introduce new shared MMU configuration table that can be used by other BSPs that call the arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache function. Demonstrate the use of the generic table with RaspberryPi.
* libbsp/sparc/.../gnatcommon.c: FormattingJoel Sherrill2013-09-301-7/+5
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* leon2/.../ckinit.c: Change get nanoseconds handler to staticJoel Sherrill2013-09-301-1/+1
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* mips/shared/.../clockdrv.c: Change get nanoseconds handler to staticJoel Sherrill2013-09-301-4/+3
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* uC5282/.../clock.c: Change get nanoseconds handler to staticJoel Sherrill2013-09-301-2/+3
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* leon3/bsppredriver.c: Add include file to warningJoel Sherrill2013-09-231-0/+1
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* leon3/.../ckinit.c: Change get nanoseconds handler to staticJoel Sherrill2013-09-231-6/+1
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* leon3/.../ckinit.c: Fix missing prototype warningsJoel Sherrill2013-09-221-1/+5
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* libbsp/shared/bspinit.c: Fix missing prototype warningsJoel Sherrill2013-09-221-3/+7
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* leon3/.../bspstart.c: Fix missing prototype warningsJoel Sherrill2013-09-221-2/+2
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* sparc/.../grcan.c: Switch to using RTEMS_COMPILER_UNUSED_ATTRIBUTEJoel Sherrill2013-09-221-8/+6
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* leon3/console.c: Fix misisng prototype issuesJoel Sherrill2013-09-211-2/+15
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* sparc/.../grcan.c: Fix multiple warningsJoel Sherrill2013-09-211-2/+8
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* sparc/.../ambapp.h: Add ambapp_get_number_apbslv_devices() prototypeJoel Sherrill2013-09-211-0/+4
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* sparc/.../occan.c: Fix missing prototype warningJoel Sherrill2013-09-211-0/+2
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* sparc/.../ambapp.h: Add ambapp_get_number_ahbslv_devices() prototypeJoel Sherrill2013-09-211-0/+6
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* sparc/../occan.c: Fix set but unused variable warningJoel Sherrill2013-09-211-2/+1
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* sparc irq-shared.c: Fix unused variable warningJoel Sherrill2013-09-211-1/+1
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* bsp/stm32f4: Add STM32F10XXX support.Christian Mauderer2013-09-1917-145/+758
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* leon3/include/bsp.h: Fix spacingJoel Sherrill2013-09-161-1/+0
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* m68k/shared/start.S: Fix spacingJoel Sherrill2013-09-161-1/+1
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* pc386/console/conscfg.c: Fix spacingJoel Sherrill2013-09-161-3/+3
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* raspberrypi.cfg: Remove CVS IdJoel Sherrill2013-09-161-2/+0
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* bsps/arm: Fix exception entriesRic Claus2013-09-161-2/+2
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* bsp/lm4f120: new BSP to support TI LM4F120 XL LaunchPad boardKarel Gardas2013-09-028-11/+121
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* bsps: Fix header includesSebastian Huber2013-08-272-9/+5
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* bsps: Add and use CLOCK_DRIVER_ISRS_PER_TICK_VALUEJoel Sherrill2013-08-262-18/+5
| | | | | | | pc386 set CLOCK_DRIVER_ISRS_PER_TICK to a string rather than a numeric value. Add CLOCK_DRIVER_ISRS_PER_TICK_VALUE and other clean up on the clock driver.
* bsp/xilinx-zynq: Add cache supportRic Claus2013-08-262-2/+888
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* bsp/csb336: Memory map update and jump to start at image start provided.Pavel Pisa2013-08-142-3/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CSB336 i.MX1/i.MXS memory map organization - SDRAM starts at address 0x08000000 but 2 MB are reserved for boot-block/loader (or other use) before RTEMS image origin/load address (that is kept from previous setup) - Caching of 30 MB of SDRAM used for RTEMS (start at 0x08200000) is changed to writeback mode which provides higher throughput. - The first 1 MB of RTEMS dedicated SDRAM is remapped to address 0 to provide area for ARM CPU exceptions table. - Internal registers and rest of the Flash (above 1 MB) are mapped one to one. Registers region is extended to 2 MB to cover eSRAM found on i.MX1 chip variant. - The first two megabytes of SDRAM unused by RTEMS are mapped with attributes to allow specific purposes. - the first MB (at address 0x08000000) is nocached to allow directly set some values read by booot-block after warm reset - the second MB (at address 0x08100000) is set for write-through caching. That allows to use memory for LCD frame-buffer without need to flush cache after each redraw. Jump to start provided at address 0x08200000 allows to load application image even as plain binary file and start it by jump to image start address. Signed-off-by: Pavel Pisa <ppisa@pikron.com>
* bsp/lm3s69xx: add macros for UART CTS/RTS pin configurationKarel Gardas2013-08-141-0/+28
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* bsps: Fix clock driver definesSebastian Huber2013-08-1410-10/+10
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* bsp: Fix CLOCK_DRIVER_USE_FAST_IDLE and CLOCK_DRIVER_ISRS_PER_TICK.Chris Johns2013-08-141-6/+6
| | | | | Use the value rather than being defined. This allows inverted logic to be used.
* bsps/arm: Use proper default priority for GICSebastian Huber2013-08-131-1/+1
| | | | | Some GIC implementations do not have the complete range of priorities. The upper bits are RAZ/WI in this case.
* bsps/i386: SMP and per-CPU thread dispatch disableSebastian Huber2013-08-091-3/+10
| | | | Interrupt support for SMP and the per-CPU thread dispatch disable level.
* bsps/i386: Revert most SMP related changesSebastian Huber2013-08-091-54/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit partially restores the _ISR_Handler code to the original version in commit b8fc2de1ce089c585da81c157ec0f24a90e484b7. A list of reverted changes follows. commit c236082873cb4a2fd42af4ca0868106e1dd65422 Author: Sebastian Huber <sebastian.huber@embedded-brains.de> Date: Tue Jul 30 15:54:53 2013 +0200 smp: Provide cache optimized Per_CPU_Control Delete _Per_CPU_Information_p. This commit was completely reverted. commit 39e51758c86754cef5ba4521c0c36578521f73d0 Author: Sebastian Huber <sebastian.huber@embedded-brains.de> Date: Fri Jun 14 14:00:38 2013 +0200 smp: Add and use _CPU_SMP_Get_current_processor() Add and use _SMP_Get_current_processor() and rtems_smp_get_current_processor(). Delete bsp_smp_interrupt_cpu(). Change type of current processor index from int to uint32_t to match _SMP_Processor_count type. This commit was completely reverted. commit e94aa61b6820e34732840139dbe3f2016c6f1e24 Author: Till Straumann <strauman@slac.stanford.edu> Date: Fri Aug 5 00:15:50 2011 +0000 2011-08-04 Till Straumann <strauman@slac.stanford.edu> * shared/irq/irq_asm.S: BUGFIX (introduced by SMP changes which moved code around, apparently): *must* store i8259 mask to frame *before* switching to IRQ stack. The code retrieves the mask after switching back to original stack. Also, the IRQ stack has no reserved space for the mask; storing it there could overwrite memory! This commit was completely reverted. commit 01f2692e338d592f363b2e27b2f62d8182d1124e Author: Jennifer Averett <Jennifer.Averett@OARcorp.com> Date: Mon Aug 1 13:41:50 2011 +0000 2011-08-01 Jennifer Averett <Jennifer.Averett@OARcorp.com> PR 1802 * shared/irq/irq_asm.S, shared/irq/irq_init.c, shared/smp/smp-imps.c, shared/smp/smp-imps.h: Add SMP support for i386. * shared/smp/getcpuid.c: New file. The parts modifying the code of _ISR_Handler were reverted. commit 66729db3115e865fa45bc4e9ab81d8266894151c Author: Joel Sherrill <joel.sherrill@OARcorp.com> Date: Wed Mar 16 20:05:17 2011 +0000 2011-03-16 Jennifer Averett <jennifer.averett@OARcorp.com> PR 1729/cpukit * shared/irq/irq_asm.S: Add next step in SMP support. This adds an allocated array of the Per_CPU structures to support multiple cpus vs a single instance of the structure which is still used if SMP support is disabled. Configuration support is also added to explicitly enable or disable SMP. But SMP can only be enabled for the CPUs which will support it initially -- SPARC and i386. With the stub BSP support, a BSP can be run as a single core SMP system from an RTEMS data structure standpoint. This commit was completely reverted.
* sparc: Make _CPU_ISR_Dispatch_disable per-CPUSebastian Huber2013-08-091-22/+20
| | | | This variable must be available for each processor in the system.
* sparc: Move _CPU_Context_switch(), etc.Sebastian Huber2013-08-091-0/+224
| | | | | | Move the _CPU_Context_switch(), _CPU_Context_restore() and _CPU_Context_switch_to_first_task_smp() code since the method to obtain the processor index is BSP specific.
* bsps/sparc: SMP and per-CPU thread dispatch disableSebastian Huber2013-08-091-10/+25
| | | | Interrupt support for SMP and per-CPU thread dispatch disable level.
* bsps/sparc: Revert most SMP related changesSebastian Huber2013-08-091-111/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As a side-effect the PR2082 is fixed with this and later changes. The commit restores the _ISR_Handler code to the original version in "cpukit/score/sparc/cpu_asm.S" in commit 6d42b4c60a4ac686489b793d5df2047c735c7c94. A list of reverted changes follows. commit c236082873cb4a2fd42af4ca0868106e1dd65422 Author: Sebastian Huber <sebastian.huber@embedded-brains.de> Date: Tue Jul 30 15:54:53 2013 +0200 smp: Provide cache optimized Per_CPU_Control Delete _Per_CPU_Information_p. This commit was completely reverted. commit e517714b7cd28807aad4c1afd8c97df72dadb4c1 Author: Jennifer Averett <jennifer.averett@oarcorp.com> Date: Tue Feb 26 12:31:23 2013 -0600 sparc: Remove dead code that was leftover from SMP development. This commit was completely reverted. commit 47a61aa16f81588f8ffb8ea5cfd1ceba3e9a867a Author: Joel Sherrill <joel.sherrill@OARcorp.com> Date: Fri Oct 7 14:35:03 2011 +0000 2011-10-07 Daniel Hellstrom <daniel@gaisler.com> PR 1933/cpukit * shared/irq_asm.S: From code inspection I have found the following issues (most SMP), and some improvements in irq_asm.S. I would need a long test with interrupts to verify the interrupt handler better, however I can not see that these patches hurt. Please see comment per hunk below, One should go through the file to indent delay-slots correctly, I have fixed some in the patch areas. An extra space is added in front of delay slots to indicate a delay slot. This commit was completely reverted. commit 0bd3f7e5d12fdbfb5bf4aa4a4169c67bfd92c988 Author: Jennifer Averett <Jennifer.Averett@OARcorp.com> Date: Thu Jul 28 17:33:07 2011 +0000 2011-07-28 Jennifer Averett <Jennifer.Averett@OARcorp.com> PR 1801 * shared/irq_asm.S: Modifications to synch the sparc with the smp working tree. This commit was completely reverted. commit 5d69cd33e9a72cf8c1a24fc9eda7f64d61f10fd1 Author: Joel Sherrill <joel.sherrill@OARcorp.com> Date: Wed Mar 16 20:05:30 2011 +0000 2011-03-16 Jennifer Averett <jennifer.averett@OARcorp.com> PR 1729/cpukit * shared/irq_asm.S: New file. The parts modifying the original code of _ISR_Handler were reverted. Only the content move remains.
* score: Per-CPU thread dispatch disable levelSebastian Huber2013-08-091-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use a per-CPU thread dispatch disable level. So instead of one global thread dispatch disable level we have now one instance per processor. This is a major performance improvement for SMP. On non-SMP configurations this may simplifiy the interrupt entry/exit code. The giant lock is still present, but it is now decoupled from the thread dispatching in _Thread_Dispatch(), _Thread_Handler(), _Thread_Restart_self() and the interrupt entry/exit. Access to the giant lock is now available via _Giant_Acquire() and _Giant_Release(). The giant lock is still implicitly acquired via _Thread_Dispatch_decrement_disable_level(). The giant lock is only acquired for high-level operations in interrupt handlers (e.g. release of a semaphore, sending of an event). As a side-effect this change fixes the lost thread dispatch necessary indication bug in _Thread_Dispatch(). A per-CPU thread dispatch disable level greatly simplifies the SMP support for the interrupt entry/exit code since no spin locks have to be acquired in this area. It is only necessary to get the current processor index and use this to calculate the address of the own per-CPU control. This reduces the interrupt latency considerably. All elements for the interrupt entry/exit code are now part of the Per_CPU_Control structure: thread dispatch disable level, ISR nest level and thread dispatch necessary. Nothing else is required (except CPU port specific stuff like on SPARC).
* bsp/pc386: Provide local outb() for elink driverSebastian Huber2013-08-091-1/+6
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* bsp/xilinx_zynq_zc706_smp: Add.Chris Johns2013-08-094-0/+14
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* Use $(EXEEXT) [defaults to "exe"] to generate binariesNick Withers2013-08-0943-58/+58
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* bsp/csb336: Fix MMU _ttbl_base location to not overlap with exception vectors.Pavel Pisa2013-08-091-3/+4
| | | | | | | | | | | | | The initial region (64 bytes) of SDRAM RTEMS image is remapped to provide overlay of the initial/ROM exceptions table. This area cannot be used for MMU mapping table. Different correctly aligned block has to be used for MMU table. Remapping of SDRAM (address 0x08200000) to address 0 is supported only on 1 MB block granularity and that is why SDRAM_VEC area has to be 1 MB aligned too but unused part of remapped region can be freely used for other purposes (as MMU tables). Signed-off-by: Pavel Pisa <ppisa@pikron.com>
* PR766: Delete __RTEMS_VIOLATE_KERNEL_VISIBILITY__Sebastian Huber2013-08-081-3/+0
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* PR766: Delete __RTEMS_APPLICATION__Sebastian Huber2013-08-081-4/+0
| | | | This define is no longer used.
* bsp/xilinx_zynq_zc706: Add.Chris Johns2013-08-082-0/+9
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* bsp/realview-pbx-a9: Enable fast idle clockSebastian Huber2013-08-061-1/+1
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* smp: Provide cache optimized Per_CPU_ControlSebastian Huber2013-07-312-13/+15
| | | | Delete _Per_CPU_Information_p.
* bsps/i386: Include missing header and fix warningsSebastian Huber2013-07-301-13/+11
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