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* bsp/arm: Report correct maximal cache line length for ARM Cortex-A + L2C-310.Pavel Pisa2016-10-021-0/+4
| | | | | Updates #2782 Updates #2783
* arm/raspberrypi: ensure that RTEMS application image can be started by U-boot.Pavel Pisa2016-10-022-1/+39
| | | | | | | | | | | | | | | | | | The current versions of U-boot start kernel/RTEMS application image with instruction and data caches enabled and it sets exception base register to new address after its self-relocation. ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */ mcr p15, 0, r0, c12, c0, 0 /* Set VBAR */ Included changes in bsp_start_hook_0 restore default state to allow RTEMS image to run after startup from newer U-boot version on Raspberry Pi. Clear interrupt enable registers in interrupt controller to ensure that RTEMS starts from well defined state. Updates #2783
* bsps/powerpc: Fix shared console driverSebastian Huber2016-07-191-13/+9
| | | | | | The Termios modes are now an emum. Do not use them in #if expressions. Update #2762.
* bsps/powerpc: Fix AltiVec enableSebastian Huber2016-07-193-0/+3
| | | | | | | There must be an isync after the mtmsr to ensure that the AltiVec is enabled for subsequent instructions. Close #2760.
* sparc: Fix window underflow trap handlerDaniel Hellstrom2016-03-241-1/+1
| | | | | | | | | | | | The window underflow trap handler used %i5 which destroyed the %o5 of the calling context. Bug introduced by 0d3b5d47429effb350448d9e9123a67db722109f. Go back to the pre 0d3b5d47429effb350448d9e9123a67db722109f behaviour and use the two unused instructions in the trap vector to optimize a bit. Close #2651.
* score: Fix simple timecounter supportSebastian Huber2016-01-2711-108/+170
| | | | Close #2502.
* bsps/arm: Fix broken switch statementSebastian Huber2016-01-181-4/+5
| | | | Close #2530.
* bsp/tms570: ensure that linker symbol comparison to NULL is not optimized out.Pavel Pisa2015-12-011-2/+12
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* bsp/tms570: unite code duplication in pinmux and clean SCI close per review ↵Premysl Houdek2015-11-183-18/+21
| | | | | | remarks. Signed-off-by: Premysl Houdek <kom541000@gmail.com>
* bsp/tms570: use common tms570ls3137.inc file for all board ling variants.Pavel Pisa2015-11-185-64/+24
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* bsp/tms570: separate Flash variants to one which boots directly and one for ↵Premysl Houdek2015-11-184-0/+57
| | | | | | | | | | | | boot loader. The default tms570ls3137_hdk variant is for building RTEMS application image starting directly from start of Flash. Variant tms570ls3137_hdk_with_loader skips 256kB at start of Flash to allow use with application loader. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* bsp/tms570: use POM only when application image does not start at address 0.Pavel Pisa2015-11-187-14/+159
| | | | | | | | | | | | | | | | | | | | | Parameters overlay module is initialized and cleared first. It is used later to replace exception target vectors only if that is required. The application loader code with CPU and SDRAM setup code has to provide well defined pattern of instructions at addresses 0x00000000 and 0x0000001f, because only data read accesses can be processed reliably by POM. The expected instruction pattern can be seen in the next example https://github.com/hornmich/tms570ls3137-hdk-sdram/blob/master/SDRAM_SCI_configuration/source/sys_intvecs.asm Comments with detailed description of code, background and reasons for selected approach have been included in TMS570 bsp startup code. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Signed-off-by: Premysl Houdek <kom541000@gmail.com>
* bsp/tms570: updated reserved space for vector overlay in internal RAMPremysl Houdek2015-11-183-4/+6
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* bsp/tms570: fixed sci driver freeze when closing terminal bugPremysl Houdek2015-11-181-3/+5
| | | | | | tms570_sci_interrupt_last_close: do not wait for old data transmit. Signed-off-by: Premysl Houdek <kom541000@gmail.com>
* bsp/tms570: Pinmux support and EMAC pin definition addedPremysl Houdek2015-11-184-1/+216
| | | | Signed-off-by: Premysl Houdek <kom541000@gmail.com>
* bsp/tms570: EMAC control header file corrected and EMAC interrupt vector addedPremysl Houdek2015-11-186-236/+295
| | | | | Signed-off-by: Premysl Houdek <kom541000@gmail.com> Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* sparc: Fix context switch on SMPDaniel Cederman2015-11-171-17/+14
| | | | | | | | | | | | | | | | | | We must not load registers (e.g. PSR) from the heir context area before the heir stopped execution. With this patch the write to PSR is divided into two steps. We first update the current window pointer and then we restore the status registers and enable traps. This allows us to move the first write to PSR to be before the write to WIM, as there is now no risk that we get an interrupt where the CWP and WIM would be inconsistent. We only need to make sure that we do not use any of the non-global registers or instructions that affects CWP for three instructions after the write. In the earlier code the non-global %o1 register was used right after the write to PSR, which required the use of three nop:s. Close #2472.
* moxiesim/configure.ac: Fix typoJoel Sherrill2015-10-201-1/+1
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* h8sim-testsuite.tcfg: Add fsdosfsname01Joel Sherrill2015-10-201-0/+1
| | | | closes #2432.
* bsp/leon3: Fix Termios context usageSebastian Huber2015-10-201-8/+3
| | | | | Only the context of the console device was used and this is wrong in case more than one APBUART device is available.
* Beaglebone: fix missing clobber in inline assembly.Marcos Diaz2015-09-101-1/+7
| | | | | | | | flush_data_cache uses R0 directly but doesn't list it as a clobbered register. Compiling with -O3 made this code break, since the function that calls flush_data_cache already uses r0. closes #2416.
* various .h files: Add missing C++ extern wrappersMartin Galvan2015-09-031-0/+4
| | | | Updates #2405.
* bsps/arm: Update due to API changesSebastian Huber2015-07-211-4/+4
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* bsp/tms570 Use bitfields instead of hard-coded valuesPremysl Houdek2015-07-204-32/+52
| | | | Signed-off-by: Premysl Houdek <kom541000@gmail.com>
* bsp/tms570: skipped 32bit field definitions and corrected single bit fieldsPremysl Houdek2015-07-2036-3298/+2641
| | | | | | | | there is no need to define access macros for field covering whole registers. In addition, BSP_FLD32 does not work right for field 32bit length. Signed-off-by: Premysl Houdek <kom541000@gmail.com>
* sh/shared/startup/bspstart.c: Add include of percpu.hJoel Sherrill2015-07-161-2/+3
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* bsp/tms570: source changes reflecting new headers.Premysl Houdek2015-07-1611-230/+335
| | | | Signed-off-by: Premysl Houdek <kom541000@gmail.com>
* bsp/tms570: fix get time resolution after infrastructure change to timecounter.Pavel Pisa2015-07-161-6/+35
| | | | | | | | | | | | | | | | | The update fixes breakage of TMS570 support after Alexander Krutwig switch of RTEMS time read to timecounter mechanism bsps: Convert clock drivers to use a timecounter Mechanism to specify odd (non 1 Mhz) time base update frequencies implemented after objections of Martin Galvan. Code is adjusted to convert RTEMS configuration parameter microseconds_per_tick to such odd base if TMS570_PREFERRED_TC_FREQUENCY is specified appropriately. Signed-off-by: Premysl Houdek <kom541000@gmail.com> Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* bsp/tms570: New/generated header files for TMS570 SoC peripherals registers.Premysl Houdek2015-07-1637-0/+14362
| | | | | | | | | | | The header files are generated by script make_header.py. Current script's version can be found at: https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python Registers offsets and fields have been extracted from reference manual. Signed-off-by: Premysl Houdek <kom541000@gmail.com>
* remaining bsp.h: Fix by hand to LIBBSP_@CPU@_@BSP_FAMILY@_BSP_HJoel Sherrill2015-07-167-14/+14
| | | | These files were left after running the script in the previous patch.
* Most bsp.h: Switch to LIBBSP_@CPU@_@BSP_FAMILY@_H for guardJoel Sherrill2015-07-1671-142/+142
| | | | | | | | | | | | | | | | | This was done by the following script run from libbsp: find * -name bsp.h | xargs -e grep -l "#ifndef.*_BSP_H" | while read b do echo $b cpu=`echo $b | cut -d'/' -f1 | tr '[:lower:]' '[:upper:]' ` bsp=`echo $b | cut -d'/' -f2 | tr '[:lower:]' '[:upper:]' ` g="LIBBSP_${cpu}_${bsp}_BSP_H" # echo $g sed -e "s/ifndef _BSP_H/ifndef ${g}/" \ -e "s/define _BSP_H/define ${g}/" \ -i $b done
* powerpc: Do not use the ATB for e500 multilibSebastian Huber2015-07-151-1/+7
| | | | | | The e500v1 has no support for the ATB. Update #2369.
* bsps/powerpc: Fix small-data area issueSebastian Huber2015-07-091-2/+4
| | | | Update #2369.
* bsps/powerpc: Provide debug and trace symbolsSebastian Huber2015-07-081-0/+3
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* bsp/qoriq: Enable branch prediction for T seriesSebastian Huber2015-07-082-0/+18
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* bsp/qoriq: Use -O2 for T seriesSebastian Huber2015-07-081-1/+1
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* RaspberryPi: Use rtems_configuration_get_microseconds_per_tick to set clock ↵Jan Sommer2015-07-071-2/+4
| | | | | | | | counter timer interrupt was hard coded to 10 ms per tick. Fix uses the setting of CONFIGURE_MICROSECONDS_PER_TICK to compute the correct start value for the counter See for more information: http://permalink.gmane.org/gmane.os.rtems.user/22691
* bsp/qoriq: Update due to API changesSebastian Huber2015-07-011-2/+2
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* bsp/mpc55xxevb: Fix configure scriptSebastian Huber2015-06-261-2/+1
| | | | | | This was the only configure.ac file with bspopts.h present in AC_CONFIG_FILES(). This somehow prevented the generation of this file leading to build errors for this BSP.
* bsps/arm: Update due to API changesSebastian Huber2015-06-261-2/+2
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* score: Simplify <rtems/system.h>Sebastian Huber2015-06-263-0/+3
| | | | | Drop the <rtems/score/percpu.h> include since this file exposes a lot of implementation details.
* bsp/gen5200: Simplify interrupt write supportSebastian Huber2015-06-241-7/+8
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* rtems: Add rtems_interrupt_local_disable|enable()Sebastian Huber2015-06-221-1/+1
| | | | | | | | Add rtems_interrupt_local_disable|enable() as suggested by Pavel Pisa to emphasize that interrupts are only disabled on the current processor. Do not define the rtems_interrupt_disable|enable|flash() macros and functions on SMP configurations since they don't ensure system wide mutual exclusion.
* pc386/console/fb*.c: Use atomics to avoid dependency on pthreadsJoel Sherrill2015-06-113-44/+45
| | | | closes #2364.
* bsps/sparc: tlib clock driver timecounter supportSebastian Huber2015-06-091-38/+56
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* sparc: Add SPARC_USE_SAFE_FP_SUPPORTSebastian Huber2015-06-091-0/+85
| | | | | | | | | | | | | | | | | | | | | | | | The SPARC ABI is a bit special with respect to the floating point context. The complete floating point context is volatile. Thus from an ABI point of view nothing needs to be saved and restored during a context switch. Instead the floating point context must be saved and restored during interrupt processing. Historically the deferred floating point switch is used for SPARC and the complete floating point context is saved and restored during a context switch to the new floating point unit owner. This is a bit dangerous since post-switch actions (e.g. signal handlers) and context switch extensions may silently corrupt the floating point context. The floating point unit is disabled for interrupt handlers. Thus in case an interrupt handler uses the floating point unit then this will result in a trap. On SMP configurations the deferred floating point switch is not supported in principle. So use here a safe floating point support. Safe means that the volatile floating point context is saved and restored around a thread dispatch issued during interrupt processing. Thus post-switch actions and context switch extensions may safely use the floating point unit. Update #2270.
* sparc: Disable FPU in interrupt contextAlexander Krutwig2015-05-301-1/+34
| | | | Update #2270.
* beagle bsp: RTC support for BBBragunath2015-05-283-0/+283
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* generic_or1k: Fix a typo in a commentHesham ALMatary2015-05-261-1/+1
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* generic_or1k: Use the correct bsp_specs fileHesham ALMatary2015-05-262-11/+6
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