| Commit message (Collapse) | Author | Age | Files | Lines |
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This has been tested on SPARC, i386, PowerPC and ARM.
Closes #2767.
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Update #2825.
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Change the testsuite configuration files to hold state information about
a test. The states are:
exclude - Do not build the test
expected-fail - The test is expected to fail
indeterminate - The test may pass or may fail
A message is printed just after the test's BEGIN message to indicate
there is a special state for the test. No state message means the test
is expected to pass.
This support requires tests are correctly written to the use standard
support to begin and end a test.
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closes #2810.
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Use _Thread_Do_dispatch() instead of _Thread_Dispatch(). Restore the
PSR[EF] state of the interrupted context via new system call
syscall_irqdis_fp in case floating-point support is enabled.
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Update #2751.
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Use a processor-specific interrupt frame during context switches in case
the executing thread is longer executes on the processor and the heir
thread is about to start execution. During this period we must not use
a thread stack for interrupt processing.
Update #2809.
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Move CPU_Interrupt_frame related defines to <rtems/score/cpuimpl.h>.
Update #2809.
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Rename SPARC-specific CPU_Minimum_stack_frame to
SPARC_Minimum_stack_frame. Rename SPARC-specific
CPU_MINIMUM_STACK_FRAME_SIZE to SPARC_MINIMUM_STACK_FRAME_SIZE.
Update #2809.
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Update #2797.
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The text and data sections may have different alignment requirements.
Support a data section alignment greater than 16.
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This makes the new Termios devices independent of device major/minor
numbers. It enables BSP independent Termios device drivers which may
reside in the cpukit domain. These drivers require an IMFS and do not
work with the device file system. However, the device file system
should go away in the future.
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Close #2684.
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Rework CPU counter support to enable use of the GR740 up-counter via
%asr22 and %asr23.
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The value of register %g1 was overwritten in a delay slot. Use
additional %g4 register.
Bug introduced by 258ad71e9626c16f30b40e06c321326636c976ff.
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The window underflow trap handler used %i5 which destroyed the %o5 of
the calling context. Bug introduced by
0d3b5d47429effb350448d9e9123a67db722109f.
Go back to the pre 0d3b5d47429effb350448d9e9123a67db722109f behaviour
and use the two unused instructions in the trap vector to optimize a
bit.
Update #2651.
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Update #2554.
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Due to GCC configuration changes, the -muser-mode option is superfluous.
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Update #2408.
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Fix for commit 76ac1ee3bba2a20ded7ea12394af0a633be25ff9.
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Update #2502.
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Notepads where a feature of RTEMS' tasks that simply functioned in
the same way as POSIX keys or threaded local storage (TLS). They were
introduced well before per task variables, which are also deprecated,
and were barely used in favor of their POSIX alternatives.
In addition to their scarce usage, Notepads took up unnecessary memory.
For each task:
- 16 32-bit integers were allocated.
- A total of 64 bytes per task per thread.
This is especially critical in low memory and safety-critical applications.
They are also defined as uint32_t, and therefore are not guaranteed to
hold a pointer.
Lastly, they are not portable solutions for SMP and uniprocessor systems,
like POSIX keys and TLS.
updates #2493.
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Use the bsp_predriver_hook() instead.
Update #2408.
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Call bsp_work_area_initialize() before bsp_start(). This allows
bsp_start() to use malloc() etc. which is beneficial for systems with a
plug-and-play hardware enumeration.
Update #2408.
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Move content to bsp_predriver_hook() functions of the BSPs.
Update #2408.
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We must not load registers (e.g. PSR) from the heir context area before
the heir stopped execution.
With this patch the write to PSR is divided into two steps. We first update
the current window pointer and then we restore the status registers and
enable traps. This allows us to move the first write to PSR to be before
the write to WIM, as there is now no risk that we get an interrupt where
the CWP and WIM would be inconsistent. We only need to make sure that we
do not use any of the non-global registers or instructions that affects
CWP for three instructions after the write.
In the earlier code the non-global %o1 register was used right after the
write to PSR, which required the use of three nop:s.
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Only the context of the console device was used and this is wrong in
case more than one APBUART device is available.
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According to the C11 and C++11 memory models only a read-modify-write
operation guarantees that we read the last value written in modification
order. Avoid the sequential consistent thread fence and instead use the
inter-processor interrupt to set the thread dispatch necessary
indicator.
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This was done by the following script run from libbsp:
find * -name bsp.h | xargs -e grep -l "#ifndef.*_BSP_H" | while read b
do
echo $b
cpu=`echo $b | cut -d'/' -f1 | tr '[:lower:]' '[:upper:]' `
bsp=`echo $b | cut -d'/' -f2 | tr '[:lower:]' '[:upper:]' `
g="LIBBSP_${cpu}_${bsp}_BSP_H"
# echo $g
sed -e "s/ifndef _BSP_H/ifndef ${g}/" \
-e "s/define _BSP_H/define ${g}/" \
-i $b
done
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